Features
- 4- 0.7V current-mode differential output pairs
- Supports Spread Injection mode and fanout mode
- Two pin selectable down spread amounts: 0.5% and 0.25%
- 50-110 MHz operation in PLL mode
- 50-400 MHz operation in Bypass mode
- Bypass mode
- Supports undriven differential outputs in PD# and SRC_STOP# modes for power management
- Output cycle-cycle jitter < 50ps
- Output to Output skew <50ps
- Phase jitter: PCIe Gen1 < 86ps peak to peak
- Phase jitter: PCIe Gen2 < 3.0/3.1ps rms
9DS400 - Block Diagram
Description
The 9DS400 is a 4-output PCIe PLL with the ability to inject spread spectrum onto the incoming differential clock, while maintaining good phase noise.
| Part Number | Status | Samples | Stock | Package | Lead Count (#) | Temp. Grade | Pb (Lead) Free | Carrier Type |
|---|---|---|---|---|---|---|---|---|
| 9DS400AGLF | Obsolete | N/A | Out of Stock | TSSOP | 28# | C | Yes | Tube |
| 9DS400AGLFT | Obsolete | N/A | Out of Stock | TSSOP | 28# | C | Yes | Reel |
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- Application NotePDF 170 KB 7WDXRDKU4E7E-5-57318 May 13, 2014
- Application NotePDF 1.9 MB 7WDXRDKU4E7E-5-57315 May 13, 2014
- Application NotePDF 495 KB 7WDXRDKU4E7E-5-57312 May 12, 2014
- Application NotePDF 442 KB 7WDXRDKU4E7E-5-57298 May 08, 2014
- Product Change NoticePDF 361 KB 7WDXRDKU4E7E-5-55130 Mar 24, 2013
- Application NotePDF 1.99 MB 7WDXRDKU4E7E-5-57242 Mar 01, 2022
- End Of Life NoticePDF 303 KB 7WDXRDKU4E7E-5-56343 Oct 27, 2013
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- Application NotePDF 1.99 MB 7WDXRDKU4E7E-5-57242 Mar 01, 2022
- Application NotePDF 170 KB 7WDXRDKU4E7E-5-57318 May 13, 2014
- Application NotePDF 1.9 MB 7WDXRDKU4E7E-5-57315 May 13, 2014View More (8)
Application Notes & White Papers (8)
- End Of Life NoticePDF 303 KB 7WDXRDKU4E7E-5-56343 Oct 27, 2013
- Product Change NoticePDF 361 KB 7WDXRDKU4E7E-5-55130 Mar 24, 2013
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This is the first video in our PCIe series. In this video, we define PCIe architectures, focusing on common and separate clock architectures. Watch the rest of the video series below where Ron will cover the impact of different timing architectures.
In this episode, Ron Wade from IDT (acquired by Renesas) explains PCIe common clocking and its impact on timing solutions. Learn about using a single clock source, fan-out buffers, and the considerations for spread spectrum and non-spread spectrum clocking in PCIe systems.
In this video, we explore PCIe with separate reference clocks and the effects of clock selection. Learn how separate reference clocks work and their impact on system performance and stability.
This video provides a high-level overview of Separate Reference Clock with Independent Spread (SRIS) architectures for PCI Express systems, additional performance requirements that this clocking architecture imposes on the reference clocks, and some system implications encountered trying to implement the architecture.
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