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Renesas Electronics Corporation

Renesas’ Timing product portfolio has been acquired by SiTime.

Datasheets, documentation, and sample orders remain available on Renesas.com through late 2026. For new designs, purchasing, support, and product inquiries, visit SiTime.com or send an email to [email protected]. Full transition to SiTime is expected by late 2026.

Features

  • Direct connection to 100Ω transmission lines; saves 24 resistors compared to standard PCIe devices
  • 55mW typical power consumption in PLL mode; minimal power consumption
  • Outputs can optionally be supplied from any voltage between 1.05V and 1.8V; maximum power savings
  • OE# pins; support DIF power management
  • HCSL-compatible differential input; can be driven by common clock sources
  • Spread spectrum tolerant; allows reduction of EMI
  • Programmable slew rate for each output; allows tuning for various line lengths
  • Programmable output amplitude; allows tuning for various application environments
  • Pin/Software selectable PLL bandwidth and PLL bypass; minimize phase jitter for each application
  • Outputs are blocked until PLL is locked; clean system start-up
  • Configuration can be accomplished with strapping pins
  • SMBus interface not required for device control
  • 3.3V tolerant SMBus interface works with legacy controllers
  • Space-saving 5mm x 5mm 40-pin VFQFPN; minimal board space
  • 3 selectable SMBus addresses; multiple devices can easily share an SMBus segment

Description

The 9DBV0641 6-output 1.8V PCIe fanout clock buffer is a member of Renesas' very-low power PCIe family. It has integrated output terminations providing Zo = 100Ω for direct connection to 100Ω transmission lines. The device has six output enable pins for clock management and three selectable SMBus addresses.

Parameters

AttributesValue
Diff. Outputs6
Diff. Output SignalingLP-HCSL
Output Freq Range (MHz)1 - 200
Diff. Inputs1
Diff. Input SignalingHCSL
Accepts Spread Spec InputYes
Power Consumption Typ (mW)53
Supply Voltage (V)1.8 - 1.8
Output TypeLP-HCSL
Diff. Termination Resistors16
Package Area (mm²)25
Battery BackupNo
Battery SealNo
CPU Supervisory Function PORNo
Crystal Frequency TrimmingNo
Frequency Out PinNo
Inputs (#)1
Input Freq (MHz)30 - 175
Divider Value1
Additive Phase Jitter Typ RMS (fs)250
FunctionZero Delay Buffer
Input TypeHCSL
Output Banks (#)1
Core Voltage (V)1.8
Output Voltage (V)0.8
Product CategoryPCI Express Clocks

Package Options

Pkg. TypePkg. Dimensions (mm)Lead Count (#)Pitch (mm)
VFQFPN5.0 x 5.0 x 0.9400.4

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