Features
- 4 - 0.7 V HCSL differential output pairs
- Phase jitter: PCIe Gen2 < 3.1 ps rms
- Phase jitter: PCIe Gen1 < 86 ps peak to peak
- Supports zero delay buffer mode and fanout mode
- Bandwidth programming available
- 50-140 MHz operation in PLL mode
- 33-400 MHz operation in Bypass mode
Description
The 9DB423 is compatible with the Intel DB400Q Differential Buffer Specification. This buffer provides 4 PCI-Express SRC or 4 QPI clocks. The 9DB423 is driven by a differential output pair from a CK410B+ or CK509B main clock generator.
| Part Number | Status | Samples | Stock | Package | Lead Count (#) | Carrier Type | Moisture Sensitivity Level (MSL) | Qty. per Reel (#) | Qty. per Carrier (#) | Package Area (mm²) | Pkg. Dimensions (mm) | Pb (Lead) Free | Pb Free Category | Temp. Range (°C) |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 9DB423BFLF | Obsolete | N/A | Out of Stock | SSOP | 28# | Tube | 1 | 0 | 47# | 54.1mm² | 10.2 x 5.3 x 1.73 | Yes | e3 Sn | 0 to 70°C |
| 9DB423BFLFT | Obsolete | N/A | Out of Stock | SSOP | 28# | Reel | 1 | 1500# | 0 | 54.1mm² | 10.2 x 5.3 x 1.73 | Yes | e3 Sn | 0 to 70°C |
| 9DB423BGLF | Obsolete | N/A | In Stock | TSSOP | 28# | Tube | 1 | 0 | 50# | 42.7mm² | 9.7 x 4.4 x 1.0 | Yes | e3 Sn | 0 to 70°C |
| 9DB423BGLFT | Obsolete | N/A | In Stock | TSSOP | 28# | Reel | 1 | 2000# | 0 | 42.7mm² | 9.7 x 4.4 x 1.0 | Yes | e3 Sn | 0 to 70°C |
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- Application NotePDF 1.9 MB 7WDXRDKU4E7E-5-57315 May 13, 2014
- Application NotePDF 495 KB 7WDXRDKU4E7E-5-57312 May 12, 2014
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- Product Change NoticePDF 361 KB 7WDXRDKU4E7E-5-55130 Mar 24, 2013
- End Of Life NoticePDF 606 KB 7WDXRDKU4E7E-5-62524 Nov 29, 2017
- End Of Life NoticePDF 599 KB 7WDXRDKU4E7E-5-61808 Aug 24, 2017
- Product Change NoticePDF 611 KB 7WDXRDKU4E7E-5-60321 Apr 14, 2016
- Product Change NoticePDF 611 KB 7WDXRDKU4E7E-5-59927 Feb 15, 2016
- Product Change NoticePDF 596 KB 7WDXRDKU4E7E-5-59884 Jan 28, 2016
- Product Change NoticePDF 544 KB 7WDXRDKU4E7E-5-59710 Nov 13, 2015
- Product Change NoticePDF 95 KB 7WDXRDKU4E7E-5-59609 Oct 22, 2015
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- Application NotePDF 1.99 MB 7WDXRDKU4E7E-5-57242 Mar 01, 2022
- Application NotePDF 1.9 MB 7WDXRDKU4E7E-5-57315 May 13, 2014
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- End Of Life NoticePDF 606 KB 7WDXRDKU4E7E-5-62524 Nov 29, 2017
- End Of Life NoticePDF 599 KB 7WDXRDKU4E7E-5-61808 Aug 24, 2017
- Product Change NoticePDF 611 KB 7WDXRDKU4E7E-5-60321 Apr 14, 2016
- Product Change NoticePDF 611 KB 7WDXRDKU4E7E-5-59927 Feb 15, 2016
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This is the first video in our PCIe series. In this video, we define PCIe architectures, focusing on common and separate clock architectures. Watch the rest of the video series below where Ron will cover the impact of different timing architectures.
In this episode, Ron Wade from IDT (acquired by Renesas) explains PCIe common clocking and its impact on timing solutions. Learn about using a single clock source, fan-out buffers, and the considerations for spread spectrum and non-spread spectrum clocking in PCIe systems.
In this video, we explore PCIe with separate reference clocks and the effects of clock selection. Learn how separate reference clocks work and their impact on system performance and stability.
This video provides a high-level overview of Separate Reference Clock with Independent Spread (SRIS) architectures for PCI Express systems, additional performance requirements that this clocking architecture imposes on the reference clocks, and some system implications encountered trying to implement the architecture.
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