Features
- 12 - 0.7 V current-mode differential output pairs.
- Supports zero delay buffer mode and fanout mode.
- Bandwidth programming available.
- 100-400 MHz operation in PLL mode
- 33-400 MHz operation in Bypass mode
- 3 selectable SMBus addresses for easy system expansion
- Spread spectrum modulation tolerant, 0 to -0.5% down spread and +/- 0.25% center spread
- Supports undriven differential outputs in Power Down Mode for power management.
- Output cycle-cycle jitter < 50 ps
- Output to output skew: 50 ps
- Phase jitter: PCIe Gen2 < 3.1 ps RMS
- Phase jitter: QPI < 0.5 ps RMS
- 64-pin TSSOP Package
- Available in RoHS compliant packaging
9DB1200C - Block Diagram
Description
The 9DB1200 is an Intel DB1200 Differential Buffer Specification device. This buffer provides 12 differential clocks at frequencies ranging from 100 MHz to 400 MHz. The 9DB1200 is driven by a differential output from a CK410B+ or CK509B main clock generator.
| Part Number | Status | Samples | Stock | Package | Lead Count (#) | Carrier Type | Moisture Sensitivity Level (MSL) | Qty. per Reel (#) | Qty. per Carrier (#) | Pb (Lead) Free | Pb Free Category | Temp. Range (°C) |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 9DB1200CGLF | Obsolete | N/A | In Stock | TSSOP | 64# | Tube | 1 | 0 | 28# | Yes | e3 Sn | 0 to 70°C |
| 9DB1200CGLFT | Obsolete | N/A | In Stock | TSSOP | 64# | Reel | 1 | 2000# | 0 | Yes | e3 Sn | 0 to 70°C |
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- End Of Life NoticePDF 859 KB Mar 24, 2022
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- Product Change NoticePDF 148 KB 7WDXRDKU4E7E-5-55894 Jul 29, 2013
- Product Change NoticePDF 361 KB 7WDXRDKU4E7E-5-55130 Mar 24, 2013
- Product Change NoticePDF 611 KB 7WDXRDKU4E7E-5-60321 Apr 14, 2016
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- Application NotePDF 1.99 MB 7WDXRDKU4E7E-5-57242 Mar 01, 2022
- Application NotePDF 170 KB 7WDXRDKU4E7E-5-57318 May 13, 2014
- Application NotePDF 1.9 MB 7WDXRDKU4E7E-5-57315 May 13, 2014View More (10)
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- End Of Life NoticePDF 859 KB Mar 24, 2022
- Product Change NoticePDF 611 KB 7WDXRDKU4E7E-5-60321 Apr 14, 2016
- Product Change NoticePDF 611 KB 7WDXRDKU4E7E-5-59927 Feb 15, 2016
- Product Change NoticePDF 596 KB 7WDXRDKU4E7E-5-59884 Jan 28, 2016
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This is the first video in our PCIe series. In this video, we define PCIe architectures, focusing on common and separate clock architectures. Watch the rest of the video series below where Ron will cover the impact of different timing architectures.
In this episode, Ron Wade from IDT (acquired by Renesas) explains PCIe common clocking and its impact on timing solutions. Learn about using a single clock source, fan-out buffers, and the considerations for spread spectrum and non-spread spectrum clocking in PCIe systems.
In this video, we explore PCIe with separate reference clocks and the effects of clock selection. Learn how separate reference clocks work and their impact on system performance and stability.
This video provides a high-level overview of Separate Reference Clock with Independent Spread (SRIS) architectures for PCI Express systems, additional performance requirements that this clocking architecture imposes on the reference clocks, and some system implications encountered trying to implement the architecture.
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