Features
- Three differential LVDS output pairs
- One differential clock input
- CLK/nCLK can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
- Input frequency range: 98MHz to 128MHz
- Output frequency range: 98MHz to 320MHz
- VCO range: 490MHz - 640MHz
- Supports PCI Express® Spread-Spectrum Clocking
- High PLL bandwidth allows for better input tracking
- PCI Express® (2.5 Gb/s) and Gen 2 (5 Gb/S) jitter compliant
- 0°C to 70°C ambient operating temperature
- Full 3.3V operating supply
- Available in lead-free (RoHS 6) packages
874003-05 - Block Diagram
Description
The 874003-05 is a high performance Differential-to-LVDS Jitter Attenuator designed for use in PCI Express® systems. In some PCI Express® systems, such as those found in desktop PCs, the PCI Express® clocks are generated from a low bandwidth, high phase noise PLL frequency synthesizer. In these systems, a jitter attenuator may be required to attenuate high frequency random and deterministic jitter components from the PLL synthesizer and from the system board. The 874003-05 has a bandwidth of 6.2MHz with <1dB peaking, easily meeting PCI Express® Gen2 PLL requirements. The 874003-05 uses IDT's 3rd Generation FemtoClock® PLL technology to achieve the lowest possible phase noise. The device is packaged in a 20 Lead TSSOP package, making it ideal for use in space constrained applications such as PCI Express® add-in cards.
| Part Number | Status | Samples | Stock | Package | Lead Count (#) | Temp. Grade | Pb (Lead) Free | Carrier Type |
|---|---|---|---|---|---|---|---|---|
| 874003BG-05LF | Obsolete | N/A | In Stock | TSSOP | 20# | C | Yes | Tube |
| 874003BG-05LFT | Obsolete | N/A | Out of Stock | TSSOP | 20# | C | Yes | Reel |
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- End Of Life NoticePDF 743 KB Jun 11, 2020
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- Product Change NoticePDF 361 KB 7WDXRDKU4E7E-5-55130 Mar 24, 2013
- Product Change NoticePDF 611 KB 7WDXRDKU4E7E-5-60321 Apr 14, 2016
- Product Change NoticePDF 611 KB 7WDXRDKU4E7E-5-59927 Feb 15, 2016
- Product Change NoticePDF 596 KB 7WDXRDKU4E7E-5-59884 Jan 28, 2016
- Product Change NoticePDF 544 KB 7WDXRDKU4E7E-5-59710 Nov 13, 2015
- Product Change NoticePDF 95 KB 7WDXRDKU4E7E-5-59609 Oct 22, 2015
- Product Change NoticePDF 50 KB 7WDXRDKU4E7E-5-59245 Jul 21, 2015
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- End Of Life NoticePDF 743 KB Jun 11, 2020
- End Of Life NoticePDF 715 KB Jun 03, 2020
- Product Change NoticePDF 611 KB 7WDXRDKU4E7E-5-60321 Apr 14, 2016
- Product Change NoticePDF 611 KB 7WDXRDKU4E7E-5-59927 Feb 15, 2016
- Product Change NoticePDF 596 KB 7WDXRDKU4E7E-5-59884 Jan 28, 2016View More (9)
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This is the first video in our PCIe series. In this video, we define PCIe architectures, focusing on common and separate clock architectures. Watch the rest of the video series below where Ron will cover the impact of different timing architectures.
In this episode, Ron Wade from IDT (acquired by Renesas) explains PCIe common clocking and its impact on timing solutions. Learn about using a single clock source, fan-out buffers, and the considerations for spread spectrum and non-spread spectrum clocking in PCIe systems.
In this video, we explore PCIe with separate reference clocks and the effects of clock selection. Learn how separate reference clocks work and their impact on system performance and stability.
This video provides a high-level overview of Separate Reference Clock with Independent Spread (SRIS) architectures for PCI Express systems, additional performance requirements that this clocking architecture imposes on the reference clocks, and some system implications encountered trying to implement the architecture.
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