Features
- Eight 0.7V differential HCSL clock output pairs
- CLK/nCLK input pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL
- Maximum output frequency: 500MHz
- Additive phase jitter, RMS: 0.09ps (typical)
- Output skew: 80ps (maximum)
- Part-to-part skew: 400ps (maximum)
- Propagation delay: 3ns (maximum)
- Full 3.3V operating supply
- -40°C to 85°C ambient operating temperature
- Available in lead-free (RoHS 6) package
85108I - Block Diagram
Description
The 85108I is a low skew, high performance 1-to-8 Differential-to-0.7V HCSL Clock Distribution Chip. The 85108I CLK, nCLK pair can accept most differential input levels and translates them to 3.3V HCSL output levels. The 85108I provides a low power, low noise, low skew, point-to-point solution for distributing HCSL clock signals. Guaranteed output and part-to-part skew specifications make the 85108I ideal for those applications demanding well defined performance and repeatability.
| Part Number | Status | Samples | Stock | Package | Lead Count (#) | Carrier Type | Moisture Sensitivity Level (MSL) | Qty. per Reel (#) | Qty. per Carrier (#) | Pb (Lead) Free | Pb Free Category | Temp. Range (°C) |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 85108AGILF | Obsolete | N/A | In Stock | TSSOP | 24# | Tube | 1 | 0 | 62# | Yes | e3 Sn | -40 to 85°C |
| 85108AGILFT | Obsolete | N/A | In Stock | TSSOP | 24# | Reel | 1 | 3000# | 0 | Yes | e3 Sn | -40 to 85°C |
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- Product BriefPDF 378 KB 7WDXRDKU4E7E-6-1169 Aug 14, 2012
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