Features
- 16-pin TSSOP and VFQFPN packages; small board footprint
- Outputs can be terminated to LVDS; can drive a wider variety of devices
- OE control pin; greater system power management
- Industrial temperature range available; supports demanding embedded applications
- Cycle-to-cycle jitter: 80ps
- Output-to-output skew <50 ps
- PCIe Gen2 phase jitter <3.0ps RMS
- Low phase noise: 12kHz to 20MHz <6ps
- For PCIe Gen3 applications, see the IDT5V41315
5V41285 Block Diagram
Description
The IDT5V41285 is a PCIe Gen2 compliant clock generator. The device has 2 differential HCSL outputs. The output frequency is selectable via select pins.
| Part Number | Status | Samples | Stock | Package | Lead Count (#) | Carrier Type | Moisture Sensitivity Level (MSL) | Qty. per Carrier (#) | Package Area (mm²) | Pitch (mm) | Pkg. Dimensions (mm) | Qty. per Reel (#) | Pb (Lead) Free | Pb Free Category | Temp. Range (°C) |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 5V41285NLGI | Obsolete | N/A | Out of Stock | VFQFPN | 16# | Tray | 3 | 624# | 9mm² | 0.5mm | 3.0 x 3.0 x 1.0 | 0 | Yes | e3 Sn | -40 to 85°C |
| 5V41285NLGI8 | Obsolete | N/A | Out of Stock | VFQFPN | 16# | Reel | 3 | 0 | 9mm² | 0.5mm | 3.0 x 3.0 x 1.0 | 2500# | Yes | e3 Sn | -40 to 85°C |
| 5V41285PGGI | Obsolete | N/A | Out of Stock | TSSOP | 16# | Tube | 1 | 96# | 22mm² | 0.65mm | 5.0 x 4.4 x 1.0 | 0 | Yes | e3 Sn | -40 to 85°C |
| 5V41285PGGI8 | Obsolete | N/A | Out of Stock | TSSOP | 16# | Reel | 1 | 0 | 22mm² | 0.65mm | 5.0 x 4.4 x 1.0 | 2500# | Yes | e3 Sn | -40 to 85°C |
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- End Of Life NoticePDF 859 KB Mar 24, 2022
- Product Change NoticePDF 2.97 MB Dec 08, 2020
- Product Change NoticePDF 5.71 MB Jun 09, 2020
- Application NotePDF 170 KB 7WDXRDKU4E7E-5-57318 May 13, 2014
- Application NotePDF 1.9 MB 7WDXRDKU4E7E-5-57315 May 13, 2014
- Application NotePDF 495 KB 7WDXRDKU4E7E-5-57312 May 12, 2014
- Application NotePDF 442 KB 7WDXRDKU4E7E-5-57298 May 08, 2014
- Application NotePDF 115 KB 7WDXRDKU4E7E-5-57294 May 07, 2014
- Application NotePDF 120 KB 7WDXRDKU4E7E-5-57289 May 06, 2014
- Application NotePDF 160 KB 7WDXRDKU4E7E-5-57287 May 06, 2014
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- Application NotePDF 1.99 MB 7WDXRDKU4E7E-5-57242 Mar 01, 2022
- Application NotePDF 170 KB 7WDXRDKU4E7E-5-57318 May 13, 2014
- Application NotePDF 1.9 MB 7WDXRDKU4E7E-5-57315 May 13, 2014View More (14)
Application Notes & White Papers (14)
- End Of Life NoticePDF 859 KB Mar 24, 2022
- Product Change NoticePDF 2.97 MB Dec 08, 2020
- Product Change NoticePDF 5.71 MB Jun 09, 2020
- Product Change NoticePDF 5.61 MB Jan 08, 2020
- Product Change NoticePDF 983 KB Jun 25, 2019View More (10)
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This is the first video in our PCIe series. In this video, we define PCIe architectures, focusing on common and separate clock architectures. Watch the rest of the video series below where Ron will cover the impact of different timing architectures.
In this episode, Ron Wade from IDT (acquired by Renesas) explains PCIe common clocking and its impact on timing solutions. Learn about using a single clock source, fan-out buffers, and the considerations for spread spectrum and non-spread spectrum clocking in PCIe systems.
In this video, we explore PCIe with separate reference clocks and the effects of clock selection. Learn how separate reference clocks work and their impact on system performance and stability.
This video provides a high-level overview of Separate Reference Clock with Independent Spread (SRIS) architectures for PCI Express systems, additional performance requirements that this clocking architecture imposes on the reference clocks, and some system implications encountered trying to implement the architecture.
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