Description
The 4286 Group is supported only for customers who have already adopted these products.
| Part Number | Status | Samples | Stock | RoHS | Package | Bit Size | RAM (KB) | Lead Count (#) | Operating Freq (Max) (MHz) | CPU | DMA | Timer | Ethernet | Temp. Range (°C) |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| M34286G2-XXXGP#V2 | Obsolete | N/A | Out of Stock | RoHS:EN RoHS:JA | LSSOP | 4 | 0.0625KB | 20# | 4MHz | 720 | No | 8-bit x 2-ch | No | -40 to +85 |
| M34286G2-XXXGP#X6 | Obsolete | N/A | Out of Stock | RoHS:EN RoHS:JA | LSSOP | 4 | 0.0625KB | 20# | 4MHz | 720 | No | 8-bit x 2-ch | No | -40 to +85 |
| M34286G2GP#V2 | Obsolete | N/A | In Stock | RoHS:EN RoHS:JA | LSSOP | 4 | 0.0625KB | 20# | 4MHz | 720 | No | 8-bit x 2-ch | No | -40 to +85 |
| M34286G2GP#X6 | Obsolete | N/A | Out of Stock | RoHS:EN RoHS:JA | LSSOP | 4 | 0.0625KB | 20# | 4MHz | 720 | No | 8-bit x 2-ch | No | -40 to +85 |
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- Application NoteAI-generated Summary: The document details the differences between the 4286 and 4283 groups, highlighting performance variations such as instruction count, execution times, I/O port functions, and operating temperature ranges. It explains pin configurations, control register differences, and added instructions exclusive to the 4286 group, including new clock division commands and voltage detection changes. Reference datasheets and technical updates are recommended for the latest information.
- Application NotePDF 125 KB REJ05B1237-0100 Rev.1.00 Aug 26, 2008AI-generated Summary: The document explains how to configure the LVD (Low Voltage Detection) and clock control for the 4286-group microcomputer. It details system clock selection using frequency divide instructions (CCK, CCK2, CCK4) and their effects on instruction and system clocks. The clock control circuit configuration is illustrated, emphasizing that frequency divide instructions execute only once. The LVD section describes how executing the CLVD instruction adjusts the reset voltage threshold from 1.5 V to 1.7 V, with timing details shown in the voltage-down detection waveform.
- Application NotePDF 154 KB REJ05B1113-0100 Rev.1.00 Dec 28, 2007AI-generated Summary: The document explains how to configure a staircase key matrix using 3-point switches for the 4283 group microcomputers operating at 4.0 MHz. It details the bit assignments and control procedures for related registers, including Timer Control Register V1 and Pulldown Control Registers PU0 and PU1. The instructions cover writing values to these registers using specific instructions to enable or disable features such as timer control and pull-down transistor activation for key-on wakeup functionality.Related Files:
- Technical Update
- Technical UpdatePDF 32 KB TN-4500-01-9501 Jan 01, 1995
Recommended Documents (1)
Datasheets (1)
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- Application NoteAI-generated Summary: The document details the differences between the 4286 and 4283 groups, highlighting performance variations such as instruction count, execution times, I/O port functions, and operating temperature ranges. It explains pin configurations, control register differences, and added instructions exclusive to the 4286 group, including new clock division commands and voltage detection changes. Reference datasheets and technical updates are recommended for the latest information.
- Application NotePDF 125 KB REJ05B1237-0100 Rev.1.00 Aug 26, 2008AI-generated Summary: The document explains how to configure the LVD (Low Voltage Detection) and clock control for the 4286-group microcomputer. It details system clock selection using frequency divide instructions (CCK, CCK2, CCK4) and their effects on instruction and system clocks. The clock control circuit configuration is illustrated, emphasizing that frequency divide instructions execute only once. The LVD section describes how executing the CLVD instruction adjusts the reset voltage threshold from 1.5 V to 1.7 V, with timing details shown in the voltage-down detection waveform.
- Application NotePDF 154 KB REJ05B1113-0100 Rev.1.00 Dec 28, 2007AI-generated Summary: The document explains how to configure a staircase key matrix using 3-point switches for the 4283 group microcomputers operating at 4.0 MHz. It details the bit assignments and control procedures for related registers, including Timer Control Register V1 and Pulldown Control Registers PU0 and PU1. The instructions cover writing values to these registers using specific instructions to enable or disable features such as timer control and pull-down transistor activation for key-on wakeup functionality.Related Files:
Application Notes & White Papers (3)
- Product Change Notice
- Product Change Notice
- Product Change Notice
Product Notices (PCN, EOL, etc) (3)
- Technical Update
- Technical UpdatePDF 32 KB TN-4500-01-9501 Jan 01, 1995
Errata & Technical Updates (3)
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