Overview
Description
The IDT ADC demo board is suitable for dynamic performance evaluations from low to high IF configuration. The FPGA eases the evaluation and analysis of the ADC dynamic and enables use of the full JESD204B feature set.
Features
- SMA connector for clock and analog input signals
- On board ARRIA II GX FPGA for JESD204B data acquisition
- Single power supply (on-board regulators)
Applications
Documentation
Featured Documentation
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| Type | Title | Date |
| Manual - Hardware | PDF 1.69 MB | |
| Manual - Software | ZIP 4.59 MB | |
| Schematic | PDF 4.20 MB | |
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