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7201

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512 x 9 Async FIFO, 5.0V

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Overview

The 7201 is a 512 x 9 dual-port FIFO memory that loads and empties data on a first-in/first-out basis. The device uses Full and Empty flags to prevent data overflow and underflow. It has a Retransmit (RT) capability that allows for reset of the read pointer to its initial position when RT is pulsed LOW. It is designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications.

7201 - Block Diagram
7201 - Block Diagram
  • Pin and functionally compatible with 720X family
  • Low power consumption
  • Ultra high speed—12ns access time
  • Asynchronous and simultaneous read and write
  • Fully expandable by both word depth and/or bit width
  • Status Flags: Empty, Half-Full, Full
  • Auto-retransmit capability
  • MIL-STD-883, Class B available in 28 pin (300 & 600 mil) Cerdip package
  • Industrial temperature range (–40C to +85C) is available
  • Available in 28 pin SOIC, PDIP (300 & 600 mil), and 32 pin PLCC packages

Documentation

Design & Development

ECAD Models

Schematic symbols, PCB footprints, and 3D CAD models from SamacSys can be found by clicking on the CAD Model links in the Product Options table. If a symbol or model isn't available, it can be requested directly from SamacSys.

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Diagram of ECAD Models

Models
Type Title Date
Model - SPICE
7201 HSPICE
Log in to Download TAR 32 KB
Model - IBIS
7201 IBIS
ZIP 9 KB
2 items

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Support Communities

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