Asynchronous FIFOs

Renesas asynchronous FIFO memory solutions allow data processing before transmission is complete, using full and empty flags to prevent data overflow and underflow. These products feature expansion logic, allowing unlimited scalability in both word size and depth. You can combine parallel asynchronous FIFOs to achieve multiple word sizes, while serial asynchronous FIFO communication simplifies data transfer.

About Asynchronous FIFO

Asynchronous FIFOs buffer data so that the first byte at the input is the first to be released at the output. Operating systems schedule CPU time for processes in the order they are received. Asynchronous FIFOs queue data and release it sequentially. Unlike synchronous FIFOs that rely on clocks, asynchronous FIFOs use asynchronous signals to synchronize CPUs with other computer hardware.

Key FIFO Parameters

Core Voltage: Supply voltage powering the dual-port RAM is typically determined by the system’s available power rails.
I/O Voltage: Voltage used for data input and output is separate from core voltage in some devices.
Density: Capacity of the asynchronous FIFO, measured in bits. Renesas offers sizes up to 512Kb.
Bus Width: Number of "lanes" used for reading and writing to the device. We offer all popular configurations.
Access Time: The time required to read the next bit from the device. Our FIFO products feature access times as low as 12ns.

Product Selector: Asynchronous FIFOs