Features
- 19 - 0.7 V current mode differential HCSL output pairs
- 8 Selectable SMBus Addresses/Multiple devices can share the same SMBus Segment
- 11 dedicated and 3 group OE# pins/Hardware control of the outputs
- PLL or bypass mode/PLL can dejitter incoming clock
- Selectable PLL bandwidth/minimizes jitter peaking in downstream PLL's
- Spread spectrum compatible, tracks spreading input clock for low EMI
- SMBus Interface, unused outputs can be disabled
- Supports undriven differential outputs in Power Down mode for power management
- Cycle-to-cycle jitter <50 ps
- Output-to-output skew < 150 ps
- PCIe Gen3 phase jitter < 1.0 ps RMS
9DB1933 - Block Diagram
Description
The 9DB1933 zero-delay buffer supports PCIe Gen3 requirements, while being backwards compatible to PCIe Gen2 and Gen1. The 9DB1933 is driven by a differential SRC output pair from an IDT 932S421, 932SQ420, or equivalent, main clock generator. It attenuates jitter on the input clock and has a selectable PLL bandwidth to maximize performance in systems with or without Spread-Spectrum clocking.
| Part Number | Status | Samples | Stock | Package | Lead Count (#) | Carrier Type | Moisture Sensitivity Level (MSL) | Qty. per Reel (#) | Qty. per Carrier (#) | Pb (Lead) Free | Pb Free Category | Temp. Range (°C) |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 9DB1933AKLF | Obsolete | N/A | Out of Stock | VFQFPN | 72# | Tray | 3 | 0 | 168# | Yes | e3 Sn | 0 to 70°C |
| 9DB1933AKLFT | Obsolete | N/A | Out of Stock | VFQFPN | 72# | Reel | 3 | 2500# | 0 | Yes | e3 Sn | 0 to 70°C |
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- End Of Life NoticePDF 938 KB Feb 28, 2022
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- Application NotePDF 170 KB 7WDXRDKU4E7E-5-57318 May 13, 2014
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- Product Change NoticePDF 103 KB 7WDXRDKU4E7E-5-55965 Aug 18, 2013
- Product Change NoticePDF 983 KB Jun 25, 2019
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- Application NotePDF 1.99 MB 7WDXRDKU4E7E-5-57242 Mar 01, 2022
- Application NotePDF 170 KB 7WDXRDKU4E7E-5-57318 May 13, 2014
- Application NotePDF 1.9 MB 7WDXRDKU4E7E-5-57315 May 13, 2014View More (10)
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- End Of Life NoticePDF 938 KB Feb 28, 2022
- End Of Life NoticePDF 909 KB Jan 20, 2022
- Product Change NoticePDF 983 KB Jun 25, 2019
- Product Change NoticePDF 583 KB 7WDXRDKU4E7E-5-61343 Dec 20, 2016
- Product Change NoticePDF 596 KB 7WDXRDKU4E7E-5-59884 Jan 28, 2016View More (11)
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- Product BriefPDF 378 KB 7WDXRDKU4E7E-6-1169 Aug 14, 2012
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This is the first video in our PCIe series. In this video, we define PCIe architectures, focusing on common and separate clock architectures. Watch the rest of the video series below where Ron will cover the impact of different timing architectures.
In this episode, Ron Wade from IDT (acquired by Renesas) explains PCIe common clocking and its impact on timing solutions. Learn about using a single clock source, fan-out buffers, and the considerations for spread spectrum and non-spread spectrum clocking in PCIe systems.
In this video, we explore PCIe with separate reference clocks and the effects of clock selection. Learn how separate reference clocks work and their impact on system performance and stability.
This video provides a high-level overview of Separate Reference Clock with Independent Spread (SRIS) architectures for PCI Express systems, additional performance requirements that this clocking architecture imposes on the reference clocks, and some system implications encountered trying to implement the architecture.
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