Features
- Guaranteed Low Skew < 125ps (max)
- Very low duty cycle distortion
- High speed propagation delay < 2.5ns. (max)
- Up to 250MHz operation
- Very low CMOS power levels
- 1.5V VDDQ for HSTL interface
- Hot insertable and over-voltage tolerant inputs
- 3-level inputs for selectable interface
- Selectable HSTL, eHSTL, 1.8V / 2.5V LVTTL, or LVEPECL input interface
- Selectable differential or single-ended inputs and ten single-ended outputs
- 2.5V VDD
- Available in TSSOP package
5T907 - Block Diagram
Description
The IDT5T907 2.5V single data rate (SDR) clock buffer is a user-selectable single-ended or differential input to ten single-ended outputs buffer built on advanced metal CMOS technology. The SDR clock buffer fanout from a single or differential input to ten single-ended outputs reduces the loading on the preceding driver and provides an efficient clock distribution network. The IDT5T907 can act as a translator from a differential HSTL, eHSTL, 1.8V/2.5V LVTTL, LVEPECL, or single-ended 1.8V/2.5V LVTTL input to HSTL, eHSTL, 1.8V/2.5V LVTTL outputs. Selectable interface is controlled by 3-level input signals that may be hard-wired to appropriate high-mid-low levels. The IDT5T907 has two output banks that can be asynchronously enabled/ disabled. Multiple power and grounds reduce noise.
| Part Number | Status | Samples | Stock | Package | Lead Count (#) | Carrier Type | Moisture Sensitivity Level (MSL) | Core Voltage (V) | Input Type | Output Skew (ps) | Output Voltage (V) | Qty. per Reel (#) | Qty. per Carrier (#) | Pb (Lead) Free | Pb Free Category | Temp. Range (°C) |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 5T907PAGI | Obsolete | N/A | Out of Stock | TSSOP | 48# | Tube | 1 | 1.8V, 2.5V | HSTL, eHSTL, LVCMOS, LVEPECL | 125ps | 1.8V, 2.5V | 0 | 39# | Yes | e3 Sn | -40 to 85°C |
| 5T907PAGI8 | Obsolete | N/A | Out of Stock | TSSOP | 48# | Reel | 1 | 2.5V | HSTL, LVTTL, LVCMOS, LVPECL | 25ps | 2.5V, 1.8V, 1.5V | 2000# | 0 | Yes | e3 Sn | -40 to 85°C |
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