パッケージ情報
| CADモデル: | View CAD Model |
| Pkg. Type: | QFN |
| Pkg. Code: | |
| Lead Count (#): | 72 |
| Pkg. Dimensions (mm): | |
| Pitch (mm): |
環境及び輸出分類情報
| Pb (Lead) Free | Yes |
| ECCN (US) | EAR99 |
| HTS (US) | 8542.39.0090 |
| Moisture Sensitivity Level (MSL) |
製品スペック
| Lead Count (#) | 72 |
| Carrier Type | Tape & Reel |
| Pb (Lead) Free | Yes |
| Temp. Range (°C) | -40 to +85°C |
| Longevity | 2040 4月 |
| Pkg. Type | QFN |
| Product Category | Jitter Attenuators |
RC32112A に関するリソース
説明
The RC32112A regenerates and distributes ultra-low jitter clock outputs and features up to six independent frequency domains that can be either locked to the external reference clock or locked to a free-run crystal or oscillator. Digital PLLs (DPLLs) support hitless reference switching between references from redundant timing sources. The device supports multiple independent timing channels for IEEE 1588 clock synthesis, SyncE clock generation, jitter attenuation, and radio clock generation including SYSREF generation for converters. Input-to-input, input-to-output, and output-to-output phase skew can all be precisely managed. The device outputs ultra-low jitter clocks that can directly synchronize SerDes running at up to 56Gbps; as well as CPRI/OBSAI, SONET/SDH ADC/DAC. The device is ideal for use in 100G/200G/400G/800G telecom switch line cards, fabric cards, and wireless small cell applications.