特長
- Low power, less than 1.4W typical
- Low jitter, less than 100fs RMS
- PCIe Gen 1-6 CC, SRIS, and SRNS support
- Up to six fractional output dividers and 12 integer output dividers
- Each fractional output divider is free-run and locked to APLL
- Each fractional output divider can be configured as NCO or DCO
- LVCMOS, LVPECL, LVDS, HCSL, CML, SSTL, and HSTL output modes supported with programmable output swing and common mode voltage
- One crystal/XO input
- Up to nine GPIO pins programmable to device select or system monitor options
- Supports 1MHz I²C, 400kHz SMBus, or 50MHz SPI serial port
- Internal non-volatile memory (up to 16 different configurations), or external serial I²C EEPROM provide default device settings on power up.
- 2.5V and 3.3V core and 1.8V, 2.5V, and 3.3V output operation
- -40 °C to +85 °C industrial temperature operation
説明
The RC22112A regenerates and distributes ultra-low jitter clock outputs and features up to six independent frequency domains that can be locked to a free-run crystal or oscillator. The device supports multiple independent reference clocks for high-speed serial links. Input-to-input, input-to-output, and output-to-output phase skew can all be precisely managed. The device outputs ultra-low-jitter clocks that can directly synchronize SerDes running at up to 56Gbps. The device is ideal for use in 100G/200G/400G/800G telecom switch fabric cards and OTN applications.
アプリケーション・ブロック図
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将来のE/Eアーキテクチャのための車載コンピュータ
高度なE/Eアーキテクチャを高い計算能力で実現する次世代車載コンピュータシステム。
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