パッケージ情報
| CADモデル: | View CAD Model |
| Pkg. Type: | CFP |
| Pkg. Code: | KBH |
| Lead Count (#): | 20 |
| Pkg. Dimensions (mm): | 12.7 x 7.5 x 0.00 |
| Pitch (mm): | 1.3 |
環境及び輸出分類情報
| Moisture Sensitivity Level (MSL) | Not Applicable |
| Pb (Lead) Free | Exempt |
| ECCN (US) | 9A515.e.1 |
| HTS (US) | 8542.39.0090 |
製品スペック
| Pkg. Type | CFP |
| Lead Count (#) | 20 |
| Carrier Type | Tray |
| Moisture Sensitivity Level (MSL) | Not Applicable |
| DLA SMD | 5962R9579401VXC |
| Pb (Lead) Free | Exempt |
| Pb Free Category | Gold Plate over compliant Undercoat-e4 |
| MOQ | 25 |
| Temp. Range (°C) | -55 to +125°C |
| DSEE (MeV·cm2/mg) | SEL free |
| Length (mm) | 12.7 |
| Pitch (mm) | 1.3 |
| Pkg. Dimensions (mm) | 12.7 x 7.5 x 0.00 |
| Qualification Level | QML Class V (space) |
| Rating | Space |
| TID HDR (krad(Si)) | 200 |
| TID LDR (krad(Si)) | ELDRS free |
| Width (mm) | 7.5 |
HCS573MS に関するリソース
説明
The Intersil HCS573MS is a radiation hardened octal transparent three-state latch with an active low output enable. The HCS573MS utilizes advanced CMOS/SOS technology. The outputs are transparent to the inputs when the Latch Enable (LE) is HIGH. When the Latch Enable (LE) goes LOW, the data is latched. The Output Enable (OE) controls the tri-state outputs. When the Output Enable (OE) is HIGH, the outputs are in the high impedance state. The latch operation is independent of the state of the Output Enable. The HCS573MS utilizes advanced CMOS/SOS technology to achieve high-speed operation. This device is a member of the radiation hardened, high-speed, CMOS/SOS logic family. The HCS573MS is supplied in a 20-lead Ceramic Flatpack (K suffix) or an SBDIP package (D suffix).
