特長
- 4- 0.7 V HCSL differential output pairs
- Phase jitter: PCIe Gen2 < 3.1 ps rms
- Phase jitter: PCIe Gen1 < 86 ps peak to peak
- Supports zero delay buffer mode and fanout mode
- Bandwidth programming available
- 50-100 MHz operation in PLL mode
- 50-400 MHz operation in Bypass mode
説明
The 9DB403 is compatible the Intel DB400 Differential Buffer Specification v2.0. This buffer provides four PCI-Express SRC clocks. The 9DB403 is driven by a differential input pair from a CK409/CK410/CK505 main clock generator.
パラメータ
| 属性 | 値 |
|---|---|
| Diff. Outputs | 4 |
| Diff. Output Signaling | HCSL |
| Output Freq Range (MHz) | 33 - 400 |
| Diff. Inputs | 1 |
| Diff. Input Signaling | HCSL |
| Accepts Spread Spec Input | Yes |
| Power Consumption Typ (mW) | 347, 380 |
| Supply Voltage (V) | 3.3 - 3.3 |
| Output Type | HCSL |
| Diff. Termination Resistors | 16 |
| Package Area (mm²) | 42.7, 54.1 |
| Battery Backup | No |
| Battery Seal | No |
| CPU Supervisory Function POR | No |
| Crystal Frequency Trimming | No |
| Frequency Out Pin | No |
| Inputs (#) | 1 |
| Input Freq (MHz) | 33 - 400 |
| Function | Zero Delay Buffer |
| Input Type | HCSL |
| Output Banks (#) | 1 |
| Core Voltage (V) | 3.3 |
| Output Voltage (V) | 3.3 |
| Product Category | PCI Express Clocks |
適用されたフィルター