特長
- Fourth-generation FemtoClock NG technology
- Universal Frequency Translator/Frequency Synthesizer
- Zero ppm frequency translation
- Two outputs, individually programmable as LVPECL or LVDS
- Both outputs may be set to use 2.5V or 3.3V output levels
- Programmable output frequency: 0.98MHz up to 1,300MHz
- Two differential inputs support the following input types: LVPECL, LVDS, LVHSTL, HCSL
- Input frequency range: 8kHz to 710MHz
- Phase Build-Out minimizes output phase change on switchover
- Crystal input frequency range: 16MHz to 40MHz
- Two factory-set register configurations for power-up default state
- Power-up default configuration pin or register selectable
- Configurations customized via One-Time Programmable ROM
- Settings may be overwritten after power-up via I2C
- I2C serial interface for register programming
- RMS phase jitter at 155.52MHz, using a 40MHz crystal (12kHz to 20MHz): 378fs (typical), Low Bandwidth mode (FracN)
- Output supply voltage modes:
- VCC/VCCA/VCCO
- 3.3V/3.3V/3.3V
- 3.3V/3.3V/2.5V
- 2.5V/2.5V/2.5V
- -40 °C to 85 °C ambient operating temperature
説明
The 8T49N205I is a highly flexible FemtoClock® NG general-purpose, low phase noise frequency translator/synthesizer with Phase Build-Out (PBO) suitable for networking and communications applications. It can generate any output frequency in the 0.98MHz to 312.5MHz range and most output frequencies in the 312.5MHz to 1,300MHz range. A wide range of input reference clocks and a range of low-cost fundamental mode crystal frequencies may be used as the source for the output frequency.
This device provides two factory-programmed default power-up configurations burned into One-Time Programmable (OTP) memory. The configuration to be used is selected by the CONFIG pin. The two configurations are specified by the customer and are programmed by Renesas during the final test phase from an on-hand stock of blank devices. The two configurations may be completely independent of one another. One usage example might be to install the device on a line card with two optional daughter cards: an OC-12 option requiring a 622.08MHz LVDS clock translated from a 19.44MHz input and a Gigabit Ethernet option requiring a 125MHz LVPECL clock translated from the same 19.44MHz input reference.
To implement other configurations, these power-up default settings can be overwritten after power-up using the I2C interface and the device can be completely reconfigured. However, these settings would have to be rewritten next time the device powers up.
To see other devices in this product family, visit the Universal Frequency Translators page.
