特長
- Three LVDS outputs
- Frequency divide select options: ÷2, ÷4, ÷8, ÷16
- IN, nIN input can accept the following differential input levels: LVPECL, LVDS, CML
- Output frequency: 2GHz
- Additive phase jitter: 0.15ps (typical)
- Output skew: 30ps (maximum), QBx, nQBx outputs
- Part-to-part skew: 250ps (maximum)
- Propagation Delay: 530ps (typical)
- Full 2.5V supply mode
- -40°C to 85°C ambient operating temperature
- Available in lead-free (RoHS 6) package
8S89872I - Block Diagram
説明
The 8S89872 is a high-speed Differential-to-LVDS Buffer/Divider with Internal Termination. The 8S89872 has a selectable ÷2, ÷4, ÷8, ÷16 output dividers. The clock input has internal termination resistors allowing it to interface with several differential signal types while minimizing the number of required external components. The device is packaged in a small, 3mm x 3mm VFQFN package, making it ideal for use on space-constrained boards.
