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ルネサス エレクトロニクス株式会社 (Renesas Electronics Corporation) - 6月はプライド月間として、LGBTQ+の権利や文化、コミュニティについて啓発する世界的な活動月間です
Low Skew, 2:1 LVPECL MUX With 1:8 Fanout And Internal Termination

パッケージ情報

CADモデル:View CAD Model
Pkg. Type:VFQFPN
Pkg. Code:NLG32
Lead Count (#):32
Pkg. Dimensions (mm):5.0 x 5.0 x 0.9
Pitch (mm):0.5

環境及び輸出分類情報

Moisture Sensitivity Level (MSL)3
Pb (Lead) FreeYes
ECCN (US)EAR99
HTS (US)8542.39.0090

製品スペック

Lead Count (#)32
Carrier TypeTray
Moisture Sensitivity Level (MSL)3
Qty. per Reel (#)0
Qty. per Carrier (#)490
Pb (Lead) FreeYes
Pb Free Categorye3 Sn
Temp. Range (°C)-40 to 85°C
Additive Phase Jitter Typ RMS (fs)170
Additive Phase Jitter Typ RMS (ps)0.17
Core Voltage (V)2.5
Divider Value1, 2, 4
FunctionBuffer, Divider
Input Freq (MHz)3000
Input TypeCML, LVDS, LVPECL
Inputs (#)1
Length (mm)5
MOQ490
Output Banks (#)3
Output Freq Range (MHz)3000
Output Skew (ps)4
Output TypeLVDS
Output Voltage (V)2.5
Outputs (#)8
Package Area (mm²)25
Pitch (mm)0.5
Pkg. Dimensions (mm)5.0 x 5.0 x 0.9
Pkg. TypeVFQFPN
Product CategoryClock Buffers & Drivers, Clock Dividers
Requires Terms and ConditionsDoes not require acceptance of Terms and Conditions
Tape & ReelNo
Thickness (mm)0.9
Width (mm)5

説明

The 8S89200I is a high-speed 1-to-8 differential-to-LVDS clock divider that is optimized for high speed and very low output skew, making it suitable for use in demanding applications such as SONET, 1 Gigabit and 10 Gigabit Ethernet, and Fibre Channel. The internally terminated differential inputs and VREF_AC pins allow other differential signal families such as LVPECL, LVDS, and CML to be easily interfaced to the input with minimal use of external components.

The device also has a selectable ÷1, ÷2, ÷4 output divider, which can allow the part to support multiple output frequencies from the same reference clock. The 8S89200I is packaged in a small 5mm x 5mm 32-pin VFQFN package which makes it ideal for use in space-constrained applications.