特長
- Accepts input frequencies ranging from 1PPS (1Hz) to 700MHz
- Two differential inputs support LVPECL, LVDS, LVHSTL, HCSL or LVCMOS reference clocks
- Generates 8 differential or 16 LVCMOS outputs
- Outputs arranged in two banks of four outputs each
- Select pins control which input drives which of two output banks
- Controlled by 3-level input pins that are 3.3V-tolerant for all core voltages
- Output type may be selected from LVPECL, LVDS or 2xLVCMOS
- Each bank supports a separate power supply of 3.3V, 2.5V or
- LVCMOS outputs are limited to 125MHz maximum and support swings of 3.3V, 2.5V, 1.8V and 1.5V
- Individual output enables and output type selection supported
- Output noise floor of –158dBc/Hz @ 156.25MHz
- Core voltage supply of 3.3V, 2.5V or 1.8V
- -40°C to +85°C ambient operating temperature
- Lead-free (RoHS 6) QFN-32 (5 × 5 mm) packaging
8P791208 - Block Diagram
説明
The 8P791208 is a low additive jitter 2:8 buffer with CMOS / differential outputs. The device takes 1 or 2 reference clocks, selects between them, using a pin selection and generates up to 8 outputs that are the same as the reference frequency. The 8P791208 supports two output banks, each with its own power supply. All outputs in one bank generate the same output frequency, but each output can be individually controlled for output type or output enable. The device can operate over the -40°C to 85°C temperature range.
パラメータ
| 属性 | 値 |
|---|---|
| Temp. Range (°C) | -40 to 85°C |
| Product Category | Clock Buffers & Drivers, RF Buffers |
パッケージオプション
| Pkg. Type | Pkg. Dimensions (mm) | Lead Count (#) | Pitch (mm) |
|---|---|---|---|
| VFQFPN | 5.0 x 5.0 x 0.9 | 32 | 0.5 |
