特長
- High speed 2:2 differential divider
- Two differential LVPECL or LVDS output pairs
- Four selectable divide combinations
- PCLKx can accept the following input levels: LVPECL, LVDS, CML
- Maximum input frequency: 2.5GHz
- Propagation delay: 0.8ns (minimum), 1.6ns (maximum)
- Output Skew: 25ps (maximum)
- Full 3.3V or 2.5V supply modes
- -40°C to 85°C ambient operating temperature
- Available in lead-free (RoHS 5) package
879S216I-02 - Block Diagram
説明
The 879S216I-02 is a Differential-to-LVPECL/ LVDS Clock Divider which can operate up to 2.5GHz. 879S216I-02 has 2 selectable differential clock inputs. The fully differential architecture and low propagation delay make it ideal for use in clock distribution circuits. 879S216I-02 can divide the input clock by ÷2, ÷4, ÷8 and ÷16. Table 4A lists all the available output dividers.
