パッケージ情報
| CADモデル: | View CAD Model |
| Pkg. Type: | TQFP |
| Pkg. Code: | PRG48 |
| Lead Count (#): | 48 |
| Pkg. Dimensions (mm): | 7.0 x 7.0 x 1.4 |
| Pitch (mm): | 0.5 |
環境及び輸出分類情報
| Moisture Sensitivity Level (MSL) | 3 |
| Pb (Lead) Free | Yes |
| ECCN (US) | EAR99 |
| HTS (US) | 8542.39.0090 |
製品スペック
| Lead Count (#) | 48 |
| Carrier Type | Tray |
| Moisture Sensitivity Level (MSL) | 3 |
| Pb (Lead) Free | Yes |
| Pb Free Category | e3 Sn |
| Temp. Range (°C) | -40 to 85°C |
| C-C Jitter Max P-P (ps) | 150 |
| Core Voltage (V) | 2.5V, 3.3V |
| Divider Value | 2, 4, 8, 16 |
| Feedback Divider | 4 - 4, 6 - 6, 8 - 8, 16 - 16 |
| Feedback Input | Yes |
| Input Freq (MHz) | 15 - 100 |
| Input Type | LVCMOS |
| Inputs (#) | 2 |
| Length (mm) | 7 |
| MOQ | 250 |
| Output Banks (#) | 2 |
| Output Freq Range (MHz) | 7.5 - 200 |
| Output Signaling | LVCMOS |
| Output Skew (ps) | 50 |
| Output Type | LVCMOS |
| Output Voltage (V) | 2.5V, 3.3V |
| Outputs (#) | 12 |
| Package Area (mm²) | 49 |
| Period Jitter Max P-P (ps) | 150 |
| Phase Jitter Max RMS (ps) | 35 |
| Pitch (mm) | 0.5 |
| Pkg. Dimensions (mm) | 7.0 x 7.0 x 1.4 |
| Pkg. Type | TQFP |
| Product Category | General Purpose Clocks |
| Prog. Clock | No |
| Qty. per Carrier (#) | 250 |
| Qty. per Reel (#) | 0 |
| Reference Output | No |
| Requires Terms and Conditions | Does not require acceptance of Terms and Conditions |
| Spread Spectrum | No |
| Tape & Reel | No |
| Thickness (mm) | 1.4 |
| VCO Max Freq (MHz) | 500 |
| VCO Min Freq (MHz) | 240 |
| Width (mm) | 7 |
879893I に関するリソース
説明
The 879893I is a PLL clock driver designed specifically for redundant clock tree designs. The device receives two LVCMOS/LVTTL clock signals from which it generates 12 new LVCMOS/LVTTL clock outputs. External PLL feedback is used to also provide zero delay buffer performance. The 879893I Intelligent Dynamic Clock Switch (IDCS) circuit continuously monitors both input CLK signals. Upon detection of a failure (CLK stuck HIGH or LOW for at least 1 period), the nALARM for that CLK will be latched (LOW). If that CLK is the primary clock, the IDCS will switch to the good secondary clock and phase/frequency alignment will occur with minimal output phase disturbance.