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Low Skew,1,÷2 Clock Generator

パッケージ情報

Pkg. Type: TQFP
Pkg. Code: PPG52
Lead Count (#): 52
Pkg. Dimensions (mm): 10.0 x 10.0 x 1.4
Pitch (mm): 0.65

環境及び輸出分類情報

Moisture Sensitivity Level (MSL) 3
Pb (Lead) Free Yes
ECCN (US) EAR99
HTS (US) 8542.39.0090

製品スペック

Lead Count (#) 52
Carrier Type Tray
Moisture Sensitivity Level (MSL) 3
Qty. per Reel (#) 0
Qty. per Carrier (#) 160
Pb (Lead) Free Yes
Pb Free Category e3 Sn
Temp. Range (°C) -40 to 85°C
Core Voltage (V) 3.3
Divider Value 1, 2
Function Buffer, Multiplexer, Divider
Input Freq (MHz) 160
Input Type CML, LVCMOS, LVPECL, SSTL
Inputs (#) 3
Length (mm) 10
MOQ 160
Output Banks (#) 4
Output Freq Range (MHz) 160
Output Skew (ps) 350
Output Type LVCMOS
Output Voltage (V) 3.3
Outputs (#) 15
Package Area (mm²) 100
Pitch (mm) 0.65
Pkg. Dimensions (mm) 10.0 x 10.0 x 1.4
Pkg. Type TQFP
Price (USD) $5.21
Requires Terms and Conditions Does not require acceptance of Terms and Conditions
Tape & Reel No
Thickness (mm) 1.4
Width (mm) 10
掲載 No

説明

The 87949I is a low skew, ÷1, ÷2 Clock Generator. The 87949I has selectable single ended clock or LVPECL clock inputs. The single ended clock input accepts LVCMOS or LVTTL input levels. The PCLK, nPCLK pair can accept LVPECL, CML, or SSTL input levels. The low impedance LVCMOS outputs are designed to drive 50? series or parallel terminated transmission lines. The effective fanout can be increased from 15 to 30 by utilizing the ability of the outputs to drive two series terminated lines. The divide select inputs, DIV_SELx, control the output frequency of each bank. The outputs can be utilized in the ÷1, ÷2 or a combination of ÷1 and ÷2 modes. The master reset input, MR/nOE, resets the internal frequency dividers and also controls the active and high impedance states of all outputs. The 87949I is characterized at 3.3V core/3.3V output. Guaranteed output and part-to-part skew characteristics make the 87949I ideal for those clock distribution applications demanding well defined performance and repeatability.