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1:5, Differential-to-LVDS Zero Delay Clock Generator

パッケージ情報

CADモデル:View CAD Model
Pkg. Type:TQFP
Pkg. Code:PRG32
Lead Count (#):32
Pkg. Dimensions (mm):7.0 x 7.0 x 1.4
Pitch (mm):0.8

環境及び輸出分類情報

Moisture Sensitivity Level (MSL)3
Pb (Lead) FreeYes
ECCN (US)EAR99
HTS (US)8542.39.0090

製品スペック

Lead Count (#)32
Carrier TypeReel
Moisture Sensitivity Level (MSL)3
Qty. per Reel (#)2000
Qty. per Carrier (#)0
Pb (Lead) FreeYes
Pb Free Categorye3 Sn
Temp. Range (°C)-40 to 85°C
C-C Jitter Max P-P (ps)30
Core Voltage (V)3.3
Feedback InputYes
Input Freq (MHz)31.25 - 700
Input TypeHCSL, HSTL, LVDS, LVPECL, SSTL
Inputs (#)2
Length (mm)7
MOQ2000
Output Banks (#)1
Output Freq Range (MHz)31.25 - 700
Output Skew (ps)35
Output TypeLVDS
Output Voltage (V)3.3
Outputs (#)5
Package Area (mm²)49
Phase Jitter Max RMS (ps)52
Pitch (mm)0.8
Pkg. Dimensions (mm)7.0 x 7.0 x 1.4
Pkg. TypeTQFP
Product CategoryZero Delay Buffers
Prog. ClockNo
Reel Size (in)13
Requires Terms and ConditionsDoes not require acceptance of Terms and Conditions
Tape & ReelYes
Thickness (mm)1.4
Width (mm)7

説明

The 8745BI is a highly versatile 1:5 LVDS Clock Generator and a member of the HiPerClockS™ family of High Performance Clock Solutions from IDT. The 8745BI has a fully integrated PLL and can be configured as zero delay buffer, multiplier or divider, and has an output frequency range of 31.25MHz to 700MHz. The Reference Divider, Feedback Divider and Output Divider are each programmable, thereby allowing for the following output-to-input frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8. The external feedback allows the device to achieve "zero delay" between the input clock and the output clocks. The PLL_SEL pin can be used to bypass the PLL for system test and debug purposes. In bypass mode, the reference clock is routed around the PLL and into the internal output dividers.