特長
- Four differential LVPECL outputs
- Differential LVPECL clock input pair
- PCLK, nPCLK pair can accept the following differential input levels: LVPECL, LVDS, CML
- Maximum output frequency: 2GHz
- Output skew: 25ps (maximum)
- Part-to-Part skew: 100ps (maximum)
- Propagation delay: 500ps (maximum)
- Additive phase jitter, RMS: 0.10ps (maximum) at 156.25MHz (12kHz to 20MHz)
- Clock enable signal synchronized to eliminate runt clock pulses
- LVPECL mode operating voltage supply range: VCC = 2.375V to 3.8V, VEE = 0V
- -40 °C to 85 °C ambient operating temperature
853S004I - Block Diagram
説明
The ICS853S004I is a low-skew, high-performance 1-to-4, 2.5V/3.3V differential-to-LVPECL fanout buffer. Guaranteed output and part-to-part skew characteristics make the ICS853S004I ideal for those applications demanding well defined performance and repeatability.
