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ルネサス エレクトロニクス株式会社 (Renesas Electronics Corporation)
Synchronization Management Unit (SMU) for IEEE 1588 and Synchronous Ethernet

パッケージ情報

CADモデル:View CAD Model
Pkg. Type:VFQFPN
Pkg. Code:NLG72
Lead Count (#):72
Pkg. Dimensions (mm):10.0 x 10.0 x 1.0
Pitch (mm):0.5

環境及び輸出分類情報

Moisture Sensitivity Level (MSL)3
Pb (Lead) FreeYes
ECCN (US)EAR99
HTS (US)8542.39.0090

製品スペック

Lead Count (#)72
Carrier TypeReel
Moisture Sensitivity Level (MSL)3
Qty. per Reel (#)2500
Qty. per Carrier (#)0
Pb (Lead) FreeYes
Pb Free Categorye3 Sn
Temp. Range (°C)-40 to 85°C
Advanced FeaturesFull SETS (ITU-T G.8264), Hitless Reference Switching, Fractional-N Input Dividers, External Sync Input, External Feedback, DCO with Physical Layer Frequency Support, LOS Inputs
ApplicationSystem Synchronizer, IEEE 1588 Synthesizer
Channels (#)3
Clock SupportG.813, G.8262, GR-1244-CORE, GR-253-CORE, G.8273.2
Core Voltage (V)1.8
Diff. Inputs4
Diff. Outputs2
Input Freq (MHz)1.0E-6 - 650
Input Freq Range Type1PPS (1 Hz), TDM, DS1, E1, SONET/SDH, Ethernet, OTN, Sync Pulse
Input TypeLVCMOS, LVPECL, LVDS
Inputs (#)6
Length (mm)10
MOQ2500
Output Freq Range (MHz)1.0E-6 - 650
Output Freq Range Type1PPS (1 Hz), TDM, DS1, E1, DS2, E3, DS3, 100BASE-T, STM-1/OC-3, STM-4/OC-12, 1000BASE-T/X, STM-16/OC-48
Output TypeLVCMOS, LVPECL, LVDS
Outputs (#)9
Package Area (mm²)100
Phase Jitter Typ RMS (ps)0.56
Pitch (mm)0.5
Pkg. Dimensions (mm)10.0 x 10.0 x 1.0
Pkg. TypeVFQFPN
Product CategoryIEEE 1588, Network Synchronization
Reel Size (in)13
Requires Terms and ConditionsDoes not require acceptance of Terms and Conditions
Tape & ReelYes
Thickness (mm)1
Width (mm)10

説明

The 82P33813 Synchronization Management Unit (SMU) provides tools to manage timing references, clock sources, and timing paths for IEEE 1588/Precision Time Protocol (PTP) and Synchronous Ethernet (SyncE) based clocks. The device supports up to three independent timing paths that control: PTP clock synthesis; SyncE clock generation; and general-purpose frequency translation. It supports physical layer timing with Digital PLLs (DPLLs) and it supports packet-based timing with Digitally Controlled Oscillators (DCOs). Input-to-input, input-to-output and output-to-output phase skew can all be precisely managed. The device outputs low-jitter clocks that can directly synchronize lower-rate Ethernet interfaces; as well as CPRI/OBSAI, SONET/SDH, and PDH interfaces and IEEE 1588 Time Stamp Units (TSUs).