特長
- Supports clock frequencies up to 100MHz
- Fast access times of 6.5ns
- Free-running CLKA and CLKB may be asynchronous or coincident
- Mailbox bypass register for each FIFO
- Programmable Almost-Full and Almost-Empty flags
- Select IDT Standard timing or First Word Fall Through timing
- Available in 120-pin TQFP packages
- Pin compatible to the lower density parts 72V36x2
- Industrial temperature range (–40C to +85C) is available
72V3672 - Block Diagram
説明
The 72V3672 Bidirectional SyncFIFO (clocked) memory is a 3.3V version of the 723672. Two independent 8K x 36 dual-port SRAM FIFOs on board each chip buffer data in opposite directions. The clocks for each port are independent of one another and can be asynchronous or coincident. The enables for each port are arranged to provide a simple bidirectional interface between microprocessors and/or buses with synchronous control.
