特長
- Clock frequencies up to 100 MHz (6.5ns access time)
- Two independent FIFOs buffer data between one bidirectional 36-bit port and two unidirectional 18-bit ports
- Programmable Almost-Empty and Almost-Full flags
- Serial or parallel programming of partial flags
- Big- or Little-Endian format for word and byte bus sizes
- Loopback mode on Port A
- Retransmit Capability
- Master Reset clears data and configures FIFO, Partial Reset clears data but retains configuration settings
- Mailbox bypass registers for each FIFO
- Auto power down minimizes power dissipation
- Available in 128-pin TQFP package
- Industrial temperature range (–40C to +85C) is available
72V3656 - Block Diagram
説明
The 72V3656 is a 2K x 36 x 2 Triple Bus sync FIFO memory that is a 3.3V version of the 723656. The enables for each port are arranged to provide a simple bidirectional interface between microprocessors and/or buses with synchronous control. This device can operate in the IDT Standard mode or First Word Fall Through mode. Two 72V3656 FIFO's can be combined with unidirectional FIFO's capable of First Word Fall Through timing (i.e. the SuperSync FIFO family) to form a depth expansion.
