特長
- Pin-compatible with the 72V2x5 SuperSync FIFOs
- Functionally compatible with the 5 Volt 722x5 family
- 10ns read/write cycle time (6.5ns access time)
- Fixed, low first word data latency time
- 5V input tolerant
- Auto power down minimizes standby power consumption
- Retransmit operation with fixed, low first word data latency time
- Empty, Full and Half-Full flags signal FIFO status
- Programmable Almost-Empty and Almost-Full flags, Easily expandable in depth and width
- Independent Read and Write clocks (permit reading and writing simultaneously)
- Available in 64-pin TQFP and STQFP packages
- Industrial temperature range (–40C to +85C) is available
72V265 - Block Diagram
説明
The 72V265 is an 16K x 18 SuperSync FIFO memory with clocked read and write controls. It's a functionally compatible version of the 72265 designed to run off a 3.3V supply for very low power consumption. The Frequency Select pin (FS) has been removed, thus it is no longer necessary to select which of the two clock inputs, RCLK or WCLK, is running at the higher frequency. SuperSync FIFOs are particularly appropriate for networking, video, telecommunications, data communications and other applications that need to buffer large amounts of data.
パラメータ
| 属性 | 値 |
|---|---|
| Core Voltage (V) | 3.3 |
| Bus Width (bits) | 18 |
| Density (Kb) | 288 |
| Pkg. Code | PNG64, PPG64 |
| Interface | Synchronous |
| I/O Type | 3.3 V LVTTL |
| I/O Frequency (MHz) | 66 - 66, 100 - 100 |
| Organization | 16K x 18 |
| Temp. Range (°C) | -40 to 85°C, 0 to 70°C |
| Architecture | Uni-directional |
