パッケージ情報
| CADモデル: | View CAD Model |
| Pkg. Type: | PDIP |
| Pkg. Code: | PD28 |
| Lead Count (#): | 28 |
| Pkg. Dimensions (mm): | 36.6 x 15.24 x 3.8 |
| Pitch (mm): | 2.54 |
環境及び輸出分類情報
| Pb (Lead) Free | No |
| Moisture Sensitivity Level (MSL) | 1 |
| ECCN (US) | |
| HTS (US) |
製品スペック
| Lead Count (#) | 28 |
| Pb (Lead) Free | No |
| Carrier Type | Tube |
| Moisture Sensitivity Level (MSL) | 1 |
| Access Time (ns) | 35 |
| Architecture | Uni-directional |
| Bus Width (bits) | 9 |
| Core Voltage (V) | 5 |
| Density (Kb) | 4 |
| Family Name | AsyncFIFO |
| I/O Type | 5.0 V TTL |
| Interface | Asynchronous |
| Length (mm) | 36.6 |
| MOQ | 143 |
| Organization | 512 x 9 |
| Package Area (mm²) | 557.8 |
| Pb Free Category | e0 |
| Pitch (mm) | 2.54 |
| Pkg. Dimensions (mm) | 36.6 x 15.24 x 3.8 |
| Pkg. Type | PDIP |
| Qty. per Carrier (#) | 13 |
| Qty. per Reel (#) | 0 |
| Requires Terms and Conditions | Does not require acceptance of Terms and Conditions |
| Tape & Reel | No |
| Temp. Range (°C) | 0 to 70°C |
| Thickness (mm) | 3.8 |
| Width (mm) | 15.24 |
| 掲載 | No |
7201 に関するリソース
説明
The 7201 is a 512 x 9 dual-port FIFO memory that loads and empties data on a first-in/first-out basis. The device uses Full and Empty flags to prevent data overflow and underflow. It has a Retransmit (RT) capability that allows for reset of the read pointer to its initial position when RT is pulsed LOW. It is designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications.