特長
- High system speed 166MHz (3.5ns clock access time)
- LBO input selects interleaved or linear burst mode
- Self-timed write cycle with global write control (GW), byte
- write enable (BWE), and byte writes (BWx)
- 3.3V core power supply
- Power down controlled by ZZ input
- 3.3V I/O supply (VDDQ)
- Available in 100-pin TQFP, 119-pin BGA and 165 fpBGA packages
説明
The 71V67603 3.3V CMOS SRAM is organized as 256K x 36. The 71V67603 SRAM contains write, data, address and control registers. The burst mode feature offers the highest level of performance to the system designer, as it can provide four cycles of data for a single address presented to the SRAM.The order of these three addresses are defined by the internal burst counter and the LBO input pin.
パラメータ
| 属性 | 値 |
|---|---|
| Density (Kb) | 9216 |
| Bus Width (bits) | 36 |
| Core Voltage (V) | 3.3 |
| Pkg. Code | PKG100 |
| Organization | 256K x 36 |
| I/O Voltage (V) | 3.3 - 3.3 |
| I/O Frequency (MHz) | 133 - 133, 150 - 150 |
| Temp. Range (°C) | -40 to 85°C, 0 to 70°C |
| Architecture | Synch Burst |
| Output Type | Pipelined |
パッケージオプション
| Pkg. Type | Pkg. Dimensions (mm) | Lead Count (#) | Pitch (mm) |
|---|---|---|---|
| TQFP | 20.0 x 14.0 x 1.4 | 100 | 0.65 |