パッケージ情報
| CADモデル: | View CAD Model |
| Pkg. Type: | SOJ |
| Pkg. Code: | PBG32 |
| Lead Count (#): | 32 |
| Pkg. Dimensions (mm): | 20.9 x 10.2 x 2.2 |
| Pitch (mm): | 1.27 |
環境及び輸出分類情報
| Pb (Lead) Free | Yes |
| Moisture Sensitivity Level (MSL) | 3 |
| ECCN (US) | EAR99 |
| HTS (US) | 8542.32.0041 |
製品スペック
| Lead Count (#) | 32 |
| Pb (Lead) Free | Yes |
| Carrier Type | Tube |
| Moisture Sensitivity Level (MSL) | 3 |
| Access Time (ns) | 10 |
| Architecture | Asynchronous |
| Bus Width (bits) | 8 |
| Core Voltage (V) | 3.3V |
| Density (Kb) | 1024 |
| I/O Voltage (V) | 3.3 - 3.3 |
| Length (mm) | 20.9 |
| MOQ | 575 |
| Organization | 128K x 8 |
| Package Area (mm²) | 213.2 |
| Pb Free Category | e3 Sn |
| Pitch (mm) | 1.27 |
| Pkg. Dimensions (mm) | 20.9 x 10.2 x 2.2 |
| Pkg. Type | SOJ |
| Qty. per Carrier (#) | 23 |
| Qty. per Reel (#) | 0 |
| Requires Terms and Conditions | Does not require acceptance of Terms and Conditions |
| Tape & Reel | No |
| Temp. Range (°C) | 0 to 70°C |
| Thickness (mm) | 2.2 |
| Width (mm) | 10.2 |
| 掲載 | No |
71V124 に関するリソース
説明
The 71V124 3.3V CMOS SRAM is organized as 128K x 8. The JEDEC center power/GND pinout reduces noise generation and improves system performance. All bidirectional inputs and outputs of the 71V124 are LVTTL-compatible and operation is from a single 3.3V supply. Fully static asynchronous circuitry is used; no clocks or refreshes are required for operation.