特長
- Dual-Port allows simultaneous access of the same memory location
- Dual chip enables allow for depth expansion without external logic
- Easily expands data bus width to 72 bits or more using the Master/Slave select when cascading more than one device
- Busy and Interrupt Flags
- On-chip port arbitration logic
- Full on-chip hardware support of semaphore signaling between ports Fully asynchronous operation from either port
- Separate byte controls for multiplexed bus and bus matching compatibility
- Includes JTAG functionality on BGA package versions only
- LVTTL-compatible, single 3.3V (±150mV) power supply for core
- LVTTL-compatible, selectable 3.3V (±150mV)/2.5V (±100mV) power supply for I/Os and control signals on each port
- Available in a 208-pin PQFP, 208-ball fpBGA and 256-ball BGA
- Industrial temperature range (–40C to +85C) is available
70V657 - Block Diagram
説明
The 70V657 is a high-speed 32K x 36 Asynchronous Dual-Port Static RAM designed to be used as a stand-alone Dual-Port RAM or as a combination MASTER/ SLAVE Dual-Port RAM for 72-bit-or-more word system. Using the IDT MASTER/SLAVE Dual-Port RAM approach in 72-bit or wider memory system applications results in full-speed, error-free operation without the need for additional discrete logic. An automatic power down feature controlled by the chip enables (either CE0 or CE1) permit the on-chip circuitry of each port to enter a very low standby power mode.
パラメータ
| 属性 | 値 |
|---|---|
| Core Voltage (V) | 3.3 |
| Bus Width (bits) | 36 |
| Density (Kb) | 1152 |
| Pkg. Code | BC256, BCG256, BF208, BFG208 |
| Interface | Async |
| I/O Type | 3.3 V LVTTL |
| Access Time (ns) | 10, 12 |
| Temp. Range (°C) | -40 to 85°C, 0 to 70°C |
| Architecture | Dual-Port |
| Organization | 32K x 36 |
| Function | Interrupt |
