特長
- Dual-port allows simultaneous access of the same memory location
- RapidWrite mode simplifies high-speed consecutive write cycles
- Dual Chip Enables allow for depth expansion without external logic
- Easily expands data bus width to 72 bits or more using the Busy Input when cascading more than one device
- Busy Input for port contention management
- Interrupt flags
- Full on-chip hardware support of semaphore signaling between ports
- Fully asynchronous operation from either port
- Separate byte controls for multiplexed bus and bus-matching compatibility
- Sleep mode inputs on both ports
- Single 2.5V (±100mV) power supply for core
- LVTTL-compatible, selectable 3.3V (±150mV) or 2.5V (±100mV) power supply for I/Os and control signals on each port
- Includes JTAG functionality
- Available in a 256-ball BGA
- Industrial temperature range (–40 °C to +85 °C) is available
説明
The 70T653M is a high-speed 256K x 36 asynchronous dual-port static RAM designed to be used as a stand-alone 18874K-bit dual-port RAM. An automatic power-down feature controlled by the Chip Enables (either CE0 or CE1) permits the on-chip circuitry of each port to enter a very low standby power mode.
パラメータ
| 属性 | 値 |
|---|---|
| Core Voltage (V) | 2.5 |
| Bus Width (bits) | 36 |
| Density (Kb) | 18432 |
| Pkg. Code | BC256, BCG256 |
| Interface | Async |
| I/O Type | 2.5 V LVTTL, 3.3 V LVTTL |
| Access Time (ns) | 10, 12 |
| Temp. Range (°C) | -40 to 85°C, 0 to 70°C |
| Architecture | Dual-Port |
| Organization | 512K x 36 |
| Function | Interrupt |
パッケージオプション
| Pkg. Type | Pkg. Dimensions (mm) | Lead Count (#) | Pitch (mm) |
|---|---|---|---|
| CABGA | 17.0 x 17.0 x 1.4 | 256 | 1 |