特長
- Reference input is 3.3V tolerant
- Four pairs of programmable skew outputs
- Low skew: 185ps same pair, 250ps all outputs
- Selectable positive or negative edge synchronization: Excellent for DSP applications
- Synchronous output enable
- Input frequency: Std: 2MHz to 160MHz
- A: 2MHz to 200MHz
- Output frequency: Std: 6MHz to 160MHz
- A: 6MHz to 200MHz
- Three-level inputs for skew and PLL range control
- Three-level inputs for feedback divide selection multiply / divide ratios of (1-6, 8, 10, 12) / (2, 4)
- PLL bypass for DC testing
- External feedback, internal loop filter
- 12mA balanced drive outputs
- Low Jitter: <100ps cycle-to-cycle
- Power-down mode
- Lock indicator
- Standard and A speed grades
- 2.5V VDD
- -40°C to 85°C ambient operating temperature
- Available in TQFP package
- Not Recommended for New Design
説明
The 5T995 is a high fanout 2.5V PLL based clock driver intended for high performance computing and data communications applications. A key feature of the programmable skew is the ability of outputs to lead or lag the REF input signal. The 5T995 has eight programmable skew outputs in four banks of 2. Skew is controlled by 3-level input signals that may be hard-wired to appropriate high-mid-low levels. The feedback input allows divide-by-functionality from 1 to 12 through the use of the DS[1:0] inputs. This provides the user with frequency multiplication from 1 to 12 without using divided outputs for feedback. When the sOE pin is held low, all the outputs are synchronously enabled. However, if sOE is held high, all the outputs except 2Q0 and 2Q1 are synchronously disabled. The LOCK output asserts to indicate when Phase Lock has been achieved. Furthermore, when PE is held high, all the outputs are synchronized with the positive edge of the REF clock input. When PE is held low, all the outputs are synchronized with the negative edge of REF. The 5T995 has LVTTL outputs with 12mA balanced drive outputs.
