特長
- Input frequency up to 200 MHz
- Advanced CMOS process
- Outputs are skew matched to within 50 ps
- Packaged in 16-pin TSSOP, Pb-free
- One PECL input to 4 PECL output clock drivers
- Operating Voltages of 3.3 V or 5 V
- Industrial temperature range
- Functional equivalent to 554-01
- Simplified passive termination network compared to 554-01
554-01A - Block Diagram
説明
The 554-01A is a low skew clock buffer with a single complimentary PECL input to four PECL outputs. Part of Renesas' Clock Blocks™ family, this is our lowest skew PECL clock buffer. The 554-01A is footprint compatible with the 554-01, but requires fewer passive components for termination thus providing a cost-saving alternative. For parts which do not require PECL inputs or outputs, see the 553 for a 1 to 4 low skew buffer, or the 552-02 for a 1 to 8 low skew buffer. For more than 8 outputs see the MK74CBxxx Buffalo™ series of clock drivers. Renesas makes many non-PLL and PLL based low skew output devices as well as Zero Delay Buffers to synchronize clocks. Contact us for all of your clocking needs.
