概要

Renesas 5P1105 Programmable buffer outputs can be individually programmed as LVDS, LVPECL, HCSL, or two LVCMOS outputs per output pair, with a crystal, LVCMOS, or differential input. There are up to four universal output pairs, as well as an LVCMOS output clock. Output frequencies range from 1 MHz to 200 MHz for LVCMOS and 1MHz to 35MHz for differential outputs. Output voltage can be individually selected (1.8V, 2.5V, or 3.3V) for each output pair. 5P1105 has four universal outputs and an LVCMOS output. The evaluation board is designed to help the evaluate the 5P1105, the latest addition to the family of programmable devices in Renesas's Timing portfolio.

5P49V5901 VersaClock 5 Evaluation Board - Top

5P49V5901 VersaClock 5 Evaluation Board - Bottom

4 Differential Outputs capable of generating any output frequency using Renesas Timing Commander^TM software
SMA connectors for outputs
When the board is connected to a PC running Renesas Timing Commander^TM software through USB, the device can be individually programmed as LVDS, LVPECL, HCSL, or two LVCMOS outputs per output pair
5P1105 has four universal outputs and an LVCMOS output.

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This video introduces the 5P1103 / 5P1105 Programmable Fanout Buffers, emphasizing their performance and flexibility. The video delves into their size, cost, and power efficiency, presenting a comprehensive analysis of these features.

Description

This is a video introduction and demonstration of the VersaClock 5 Evaluation Board. This device uses Renesas's Timing Commander™ software platform, allowing engineers to configure and program their devices with an intuitive, time-saving graphical user interface (GUI).

The 5P49V5901 is an in-system programmable clock generator featuring four universal output pairs capable of producing independent frequencies up to 350 MHz in various output types. With RMS phase jitter less than 0.7 picoseconds over the full 12 kHz to 20 MHz integration range, the new device meets the stringent jitter requirements of PCI Express® Gen 1/2/3, USB 3.0, and 1G/10G Ethernet. The high-performance clock generator operates at less than 100 mW core power (50 percent lower than competing devices), helping to ease system thermal constraints, reduce operating power expenses, and maximize battery life.

The 5P49V5901's four universal output pairs are each independently configurable as HCSL, LVPECL, LVDS, or dual LVCMOS outputs. The fractional output dividers driving each output pair are easily programmed via I2C while the device is operating in the system, lending itself to system tuning and margin testing. Unlimited in-system reprogramming is possible via I2C, whereas four banks of one-time programmable non-volatile memory provide flexibility for multi-project inventory consolidation or design changes in field or production units. Upon request, devices may be factory-programmed to the customer's desired configuration.

Presented by Shudong Zheng, Sr. Design Engineer at IDT. For more information about Renesas's VersaClock 5, visit our VersaClock5 page.

Transcript

Hi, my name is Shudong Zhen. I'm the application engineer in IDT timing group. Today, I'm going to introduce you to the VersaClock 5 Evaluation Board. The board comes in a box, a full package. First of all, of course, this board is out of the static bag.

This is the board with the USB cable. So, this is the board. It has two power systems. As you can see, there are two red banana jacks and one black banana jack for the power return. Also, we support the USB power for the whole board.

For this demonstration, I'm going to use the USB power because this is the first power supply we recommend you to use. It's easy. You don't need to connect the cables to the bench power supply.

Now here, we have the VersaClock 5 timing commander GUI opened up in a computer and right now, the board is not connected to the software. So, you can see there's no sign of communication between the software and the board. Now, let's make a connection to the board. The USB cable that comes with the box and one side, plug into the USB connector of the PC and then the other side goes to the board, the mini USB connector.

Now, up until this point, we're still not seeing the connection because we need to click on this chips symbol sign to make the connection but before I do that, I want to show you the default frequency output from the board.

Now, here is the scope, with the SMA connector cables. I'm going to connect these to the output one of the board. As you can see, on the scope screen, there is already 100 MHz LVCMOS differential output already, as you can see. So, this is the default output from the chip, output one and one B. As you can see, if I disconnect the power, there's no output and then when I connect to the power, the output is coming out right away. That's the default output.

Now, on this very same output, if I, in the VersaClock 5 Timing Commander GUI, if I change that output to 125 MHz, you're going to see the frequency change. Right now, this is the point I need to make the connection to the board so that the configuration can be downloaded into the chip.

So, first of all, click on the chip sign and then, as you can see, this area becomes green, which is a sign of successful connection to the board. Now, on the right side of this sign, if you hover the mouse onto the sign, you can see write all registers to the chip. Right now, I have 25 megaHertz crystal input. I entered 25 into the input frequency box and then, on the output frequency box for output one, I have entered 125 MHz.

Now, once I write this configuration into the chip, you're going to see the change on the screen, on the scope screen. Now, the GUI shows WriteAll has completed. The scope screen should have shown the 125 MHz output from the default 100 MHz. So, the configuration of the board is very easy once we have a good connection. The desired output frequency can be immediately displayed.

We can also use the bench power supply to power the board. These two red banana jacks and the one black banana jack are for the bench power supply. If we use this cable from the bench power supply to make the connection... So, this is a green cable but still, we use it as a power supply, 3.3 volts and this is for the return, the power return. At the same time, the USB cable can still be connected for the data communication. The power supply is provided by the connectors, although we need to make the jumpers. We know the jumpers will make the selections between the USB power and the jack power. In this case, for example, as you can see, the labels on this connector, the VDDD_J means the power is coming from the jack. So, we need to move the connector into the left side and it's the same move for all the other jumpers, to make the power supply switch. That's for the power supply and then I think that concludes the introduction to the VersaClock 5 Evaluation Board. Thank you very much for you time to listen to this video. Thank you.

Description

VersaClock® 5 is a low-power programmable clock generator with best-in-class jitter performance with less than 0.7psec RMS phase jitter from 12KHz to 20MHz. The highly integrated device consolidates four differential or eight single-ended clock generators and can store up to four different configuration settings, helping to minimize board space and bill-of-materials. The high-performance clock generator operates at less than 100mW core power (50 percent lower than competing devices), helping to ease system thermal constraints and reduce operating power expenses.

VersaClock 5 can take a crystal or a clock input. It has 4 fractional output dividers which allow the programming of 4 independent frequencies up to 350MHz. The four universal output pairs are independently configurable as HCSL, LVPECL, LVDS, or dual LVCMOS outputs. It also features a reference clock output. The fractional output dividers driving each output pair are easily programmed via I2C while the device is operating in the system, lending itself to system tuning and margin testing. Unlimited in-system reprogramming is possible via I2C, whereas four banks of one-time programmable non-volatile memory provide flexibility for multi-project inventory consolidation or design changes in field or production units. Upon request, devices may be factory-programmed to the customer's desired configuration.

Presented by Baljit Chandhoke, Product Marketing Manager at Integrated Device Technology, Inc. To learn more about Renesas's VersaClock programmable clock generators, visit our page.

Transcript

Hello, my name is Baljit Chandhoke and I’m the Product Marketing Manager of Timing Products at IDT. Today, I will give you a brief introduction of our new low power programmable clock family, VersaClock 5.

VersaClock 5 is a low power, programmable clock generator with best in class jitter performance with less than .7ps RMS phase jitter from 12KHZ to 20MHz. The highly integrated device consolidates four differential or eight single-ended clock generators and can store up to four different configuration settings, helping to minimize board space and bill of materials. It also has a buffered reference clock output.

The high performance clock generator operates at less than 100mW core power, 50% lower than competing devices, with typical total device power of 300mW with all outputs operational, helping to ease system tunnel constraints and reduce operating power expenses. VersaClock 5 has four universal output pairs. Each output pair can be configured as HCSL, LVPECL, LVDS, or two LVCMOS outputs. VersaClock 5 has in-system, programmable clock generator via I2C as well as IDT’s Timing Commander Software.

This slide shows the block diagram of VersaClock 5. VersaClock 5 can take a crystal or clock input. It has four fractional output dividers, which allow programming of four independent frequencies, up to 350MHz. The four universal output pairs are independently configurable as HCSL, LVPECL, LVDS or dual LVCS outputs. It also features a reference clock output. The fractional output dividers driving each output pair are easily programmed via I2C, while the device is operating in the system, enabling system tuning and margin testing. Unlimited in-system reprogramming is possible via I2C, whereas four banks of one-time programmable non-volatile memory provide flexibility for multi-project imagery consolidation or design changes in field. Upon request, the devices may be factory programmed to customer’s desired configuration.

VersaClock 5 has excellent phase jitter performance with 610fsec RMS phase jitter, as shown on the phase noise plot. With RMS phase jitter less than .7ps or the full 12KHz to 20MHz integration range, the new device meets the stringent jitter requirements of PCI Express Gen 1, Gen 2, and Gen 3, as well as USB3.0 and 1G/10G Ethernet.

IDT’s new Timing Commander Software platform enables customers to configure program VersaClock 5 with an intuitive and flexible graphical user interface, as you see on the slide. You can program the four fractional output dividers, providing four independent output frequencies with 0 ppm error. You can configure universal output pairs as differential LVDs, HCSL, LVPECL, or two single unit outputs, as well as program each output independently with spread spectrum, if needed.

VersaClock 5 is useful in high-end consumer applications, networking applications, computing applications, industrial communications, broadcast radio and medical applications.

The block diagram shows a typical application of VersaClock 5, which has a 125 LVPECL output for gigabit Ethernet, a 156.25MHz LVDS output for 10 gig Ethernet and a 100MHz HCSL output for PCIe Gen3, as well as a 25MHz reference output. With all the different outputs operational and the cross-talk – including the cross-talk, we get 700fsec integrated phase jitter from 12KHz to 20MHz. The key application issues solved by VersaClock 5 are shown on the slide.

In summary, VersaClock 5 is a low-power, programmable clock generator with best-in-class performance and design flexibility. It has excellent phase jitter performance. Our wide range of frequencies provides design flexibility with less than .7ps RMS phase jitter from 12KHz to 20MHz. VersaClock 5 has significantly less power consumption, which enables easing thermal constraints in the system. IDT VersaClock 5 programmable clocks are ideal clocking solutions for a wide range of applications replacing crystal oscillators, clock generators – allowing for in-system programming, saving BOM and board space, as well as improving time to market and shortening design time. IDT VersaClock 5 provides industry’s most versatile, low-power clock generation solution for consumer, computing, industrial, communications and networking applications.

We have complete product support for VersaClock 5. We have a product brief, product data sheet, programming guide, elevation board with user’s manual, Timing Commander Software with user’s manual, product radio reference schematic available at the link shown on the slide.

Thank you for your time.


分類	タイトル	日時
製品概要	5P1103/5P1105 Programmable Universal Output Buffers PDF 832 KB	2015年4月29日
マニュアル－ソフトウェア	Timing Commander Software for Programmable Buffers PDF 1011 KB	2015年4月20日
マニュアル－ハードウェア	Programmable Clock Buffer 5P1105/5P1103 Evaluation Board PDF 721 KB	2015年4月17日
回路図	5P1105 Reference Schematic PDF 31 KB	2015年4月13日
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EVK-5P1105

Evaluation Board for 5P1105 Universal Output Buffer

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