Zero-delay buffers (ZDB) provide a synchronous copy (no propagation delay) of the input clock at the outputs, usually without frequency translation. The Renesas ZDBs are PLL-based devices that regenerate the input clock signal with fanout to drive multiple loads offering various signal levels, including LVPECL, LVDS, HCSL, CML, HSTL, SSTL, or LVCMOS. ZDBs are ideal for applications requiring synchronized clocking for FPGAs, CPUs, logic, and synchronous memory.

Most zero-delay buffers allow the delay through the device to be adjusted through an external feedback path. This allows precise control of the timing of the clock signals to the loads. Simple frequency translation is possible with a ZDB when a single divider is used for all outputs, including feedback output, to maintain clock synchronization.

Hint: If more than one unique output frequency is required (eg. 100MHz and 125MHz), make use of the “Output Banks” parametric selector. Each bank corresponds to a unique output frequency.

Industry-Leading Zero-Delay Buffer Solutions

The Renesas zero-delay buffer (ZDB) IC families are available with a wide range of options and features. Differential outputs such as LVPECL, LVDS, HCSL, CML, HSTL, SSTL, as well as selectable outputs, are supported for output frequencies up to 3.2GHz and single-ended LVCMOS outputs for frequencies up to 350MHz. In addition, Renesas' PLL portfolio has devices supporting supply voltages from 1.2V up to 3.3V and that are available in the commercial and industrial temperature ranges.

Using a Renesas PLL product has many benefits. Reducing the number of quartz crystals on a board improves reliability because crystals are highly susceptible to shock and vibration. Using a clock signal generator also reduces a customer's board cost and space, bill of materials (BOM) and inventory levels by replacing multiple crystals and oscillators with one device. They are ideal for use in a large variety of systems, from personal computers to consumer electronics or industrial systems, as well as high-performance networking and communications systems.

Selecting a Zero-Delay Buffer (ZDB)

There are many important factors when choosing a ZDB for a particular application. The following parameters will give users a basic starting point to narrow down the potential solutions:

  • # of outputs: choose a ZDB with enough outputs to simplify your clock tree. Fewer components simplify the design and procurement process for faster time to market, and can even improve reliability for better production yields. Renesas offers some of the industry’s most integrated solutions for highly-complex systems, along with right-sized solutions for those that fall in between.
  • Output type: this is the signaling type of the output that is required of the zero-delay buffer. Renesas offers LVPECL, LVDS, HCSL, CML, HSTL, SSTL, or LVCMOS.
  • Input/Output frequency range: the valid range of input and output frequencies. Renesas offers zero-delay buffers to address the frequency needs of all popular applications.
  • Core voltage: the supply voltage used to power the ZDB. This is typically defined by the power rails available in the system, and often has implications on voltage levels of the output. Renesas zero-delay buffers are offered in voltages from 3.3V down to 1.5V.

Documentation

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Overview

Videos & Training

Zero-Delay Clock Buffers by IDT

Description

Brief overview of IDT's zero-delay buffers. Zero-delay buffers (ZDB) are ideal for applications requiring synchronized clocking for FPGAs, CPUs, logic and synchronous memory. Zero-delay buffers are PLL-based devices that regenerate the input clock signal with fanout to drive multiple loads. Most devices allow the delay through the device to be adjusted through an external feedback path. This allows precise control of the timing of the clock signals to the loads. Zero-delay buffers provide a synchronous copy of the input clock at the outputs, usually without frequency translation. Simple frequency translation is possible when a single divider is used for all outputs, including feedback output, to maintain clock synchronization.Presented by Vik Chaudhry, technical marketing manager at IDT. For more information about IDT's rich portfolio of clock IC timing solutions, visit www.idt.com/go/clocks.

 

Transcript

Thank you for joining us for an overview of IDT's fanout buffers. My name Vik Chaudhry. I'm Marketing Manager for IDT's timing products. 
 
We also have zero delay buffers in our portfolio. A zero delay buffer is a PLL-based device that provides an output that is in phase alignment with the input signal. In this category of devices we have parts with multiple outputs, different levels of inputs and outputs, and different divider ratios. Designers like these types of devices when they want really tight control over timing of their board. 
 
IDT has a very large portfolio of fanout and clock distribution devices. To make it easy to select these parts, we have developed collateral that can be used. This collateral is located on the IDT website under clock and timing products. If you look under fanout buffers and dividers, you will see this collateral available.
 
We also have an excellent application support for all the clocks and clock distribution devices. Most of our products include IBIS models. We also have application notes for various termination schemes, filter recommendations, and we also review schematics. If you have any questions, please feel free to either drop us an e-mail at tsd-applications@IDT.com or clocks@IDT.com
 
Thank you for choosing IDT timing products.