Features
- SRAM-type interface
- Double-data-rate architecture
- PLL circuitry
- Cycle time: 1.875 ns @ tRC = 15 ns 2.5 ns @ tRC = 15 ns 2.5 ns @ tRC = 20 ns 3.3 ns @ tRC = 20 ns
- Non-multiplexed addresses
- Multiplexing option is available.
- Data mask for WRITE commands
- Differential input clocks (CK and CK#)
- Differential input data clocks (DK and DK#)
- Data valid signal (QVLD)
- Programmable burst length: 2 / 4 / 8 (x18)
- User programmable impedance output (25 Ω - 60 Ω)
- JTAG boundary scan
Description
The µPD48576118F1 is a 33, 554, 432 word by 18 bit synchronous double data rate Low Latency RAM fabricated with advanced CMOS technology using one-transistor memory cell. The µPD48576118F1 integrate unique synchronous peripheral circuitry and a burst counter. All input registers controlled by an input clock pair (CK and CK#) are latched on the positive edge of CK and CK#. These products are suitable for application which require synchronous operation, High-Speed, low voltage, high density and wide bit configuration.
| Part Number | Status | Samples | Stock | RoHS | Package | Carrier Type |
|---|---|---|---|---|---|---|
| UPD48576118F1-E24-DW1-A | Obsolete | N/A | In Stock | RoHS:EN RoHS:JA | TFBGA | Tray |
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