Features
- High Accuracy: VREF = 2.495 V ± 2 %
- Low Temperature Coefficient: ∆VREF/∆T ≤ 100 ppm/°C
- Adjustable Output Voltage by two External Resistors: VREF ≤ VO ≤ 36 V
- Low Dynamic Impedance: | ZKA | = 0.1 ΩTYP.
Description
The µPC1093 are adjustable precision shunt regulators with guaranteed thermal stability. The output voltage can be set to any value between reference voltage (2. 495 V) and 36 V by two external resistors. These ICs can apply to error amplifier of switching regulators.
Parameters
| Attributes | Value |
|---|---|
| SYNCH Capability | No |
Application Block Diagrams
 | Bedside Monitor Power Supply Reliable power supply design with battery backup and isolated supplies for bedside monitoring systems. |
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| Part Number | Status | Samples | Longevity | Stock | RoHS | Package | Budgetary Price (USD) | Country of Assembly | Country of Wafer Fabrication |
|---|---|---|---|---|---|---|---|---|---|
| UPC1093T-1-E1-A | Active | Available | Out of Stock | Contact | Package | 1ku | $0.38 | JAPAN | JAPAN | |
| UPC1093T-1-E1-AZ | Active | N/A | Out of Stock | Contact | Package | 1ku | $0.387 | JAPAN | JAPAN | |
| UPC1093T-1-E2-A | Active | Available | Out of Stock | Contact | Package | 1ku | $0.52 | JAPAN | JAPAN | |
| UPC1093T-1-E2-AZ | Active | N/A | In Stock | Contact | Package | 1ku | $0.522 | JAPAN | JAPAN | |
| UPC1093T-AZ | Active | N/A | Out of Stock | Contact | Package | 1ku | $0.55 | JAPAN | JAPAN | |
| UPC1093T-E1-A | Active | Available | 2030 Mar | Out of Stock | Contact | Package | 1ku | $0.4 | JAPAN | JAPAN |
| UPC1093T-E1-AZ | Active | N/A | In Stock | Contact | Package | 1ku | $0.412 | JAPAN | JAPAN | |
| UPC1093T-E2-AZ | Active | N/A | In Stock | Contact | Package | 1ku | $0.387 | JAPAN | JAPAN | |
| UPC1093T-2-E1-AZ | Obsolete | N/A | Out of Stock | RoHS:EN RoHS:JA | Package | ||||
| UPC1093T-2-E2-AZ | Obsolete | N/A | Out of Stock | RoHS:EN RoHS:JA | Package | ||||
| UPC1093T-E1 | Obsolete | N/A | Out of Stock | RoHS:EN RoHS:JA | Package |
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- Application NotePDF 1.3 MB R19AN0015ED0102 Rev.1.02 Jul 01, 2013AI-generated Summary: The document provides layout recommendations and design rules for a dual port Ethernet PHY device supporting 10Base-T, 100Base-TX, and 100Base-FX. It covers strap pin configuration options for initial start-up settings, detailing the use of pull-up and pull-down resistors, including recommended resistor values and schematic examples. The strap pins function only during power-up or reset, with internal and external resistor configurations advised for noise immunity. Additional chapters address media interfaces, power supply layout, clock input, LED control, and unused pins.
- Application NotePDF 1.21 MB R19AN0014ED0102 Rev.1.02 Jul 01, 2013AI-generated Summary: The document provides layout recommendations and design rules for Dual PHY and Single Channel PHY ASSP devices. It covers strap pin configuration options for initial start-up settings, including pull-up and pull-down resistor values and configurations to ensure stable operation in noisy environments. The layout guidelines include power supply design, differential pair routing, media-dependent interfaces, MAC interfaces, and clock input circuits. Examples and tables illustrate resistor values and schematic configurations for strap pins.
- Application NotePDF 397 KB an1684 Jan 19, 2004AI-generated Summary: The document outlines important legal disclaimers and usage guidelines for semiconductor products. It emphasizes user responsibility for product design and safety, disclaims liability for damages, and clarifies no intellectual property licenses are granted. Products are categorized by quality grades with specific application recommendations. Users must comply with laws, avoid unauthorized modifications, and ensure safe use within specified conditions. Contact details for Renesas Electronics sales offices worldwide are provided.
- Application NotePDF 509 KB an1681 Jan 19, 2004AI-generated Summary: The document explains grounding techniques for PCB layouts using a dual op amp example on a single-layer copper board. It compares three grounding schemes: a center spine ground trace, an outer ground plane, and a split/star ground plane, highlighting the benefits of single-point grounding to minimize noise and antenna effects. It emphasizes following current paths, minimizing loop lengths, and ensuring close forward and return paths to reduce interference. The document also includes disclaimers on product use, quality grades, safety, and legal compliance.
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