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SLG47920

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Low-Power FPGA with 2240 LUTs, 32 GPIOs, LVDS Support, OTP/SPI Config, in Compact Package for Space-Constrained Digital Designs

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Features

  • Dense array of configurable logic
    • 2240 5-bit LUTs
    • 2240 D-type flip flops (DFFs)
    • 10kb distributed memory
    • 64kb block random access memory (BRAM)
  • Power supply domains
    • Two separate domains (16 GPIOs per domain)
    • VDDIO0 and VDDIO1: 1.71V to 3.465V
    • VDDC: 1.1V ± 5%
  • Clocking
    • High-frequency oscillator
      • 50MHz high-frequency oscillator
    • Oscillator post divider
      • Divide oscillator clock by a power of 2 (range 1 to 128)
      • Two independent outputs
    • Phase-locked loop (PLL)
      • Input from an external source, internal oscillator, or LVDS differential clock
  • Power-on reset (POR)
  • Flexible power-consumption control
    • FPGA core power control
    • Clock sources power control
    • BRAM deep-sleep/power-gated modes
  • General-purpose IOs
    • 32 GPIOs
    • Flexible configuration options
      • Selectable drive strength (4/8/12mA)
      • Optional pull-up – 1x or 2x
      • Optional pull-up control from the FPGA core
      • Optional Schmitt trigger input
    • Six LVDS-capable GPIOs (three true-LVDS pairs up to 100Mbps)
    • Fast routing capability between pairs of GPIO located in different IO voltage domains
  • Bitstream security features
    • CRC integrity check
    • AES decryption
  • Configuration options
    • OTP mode – Load from built-in OTP memory
    • SPI Controller (Master) mode – Load from external Flash memory
    • SPI Target (Slave) mode – Load from external source (MCU host)
  • Boot control logic: Can address up to 16 different bitstreams from external memory
  • Two idle low-power modes
    • Sleep mode when configuration is being retained and no device re-configuration is needed
    • Reset mode when device re-configuration is required after exit from this mode
    • Possibility to retain GPIOs and BRAM states in both low-power modes
    • Low power consumption in both modes (< 85µA)
  • Operating temperature range: -40°C to 85°C
  • RoHS-compliant/Halogen-free
  • Available package
    • SLG47920V: 40-pin QFN, 5.0mm x 5.0mm, 0.4mm pitch
Find Other Products in ForgeFPGA Low-Density FPGAs
SLG47920/SLG47921 Block Diagram
SLG47920/SLG47921 Block Diagram

Description

The SLG47920 is a small, low-power device for common FPGA applications. Users create a circuit design by programming the one-time programmable (OTP) non-volatile memory (NVM) or providing a bitstream through an SPI interface to configure the FPGA core, the IO pins, and the macrocells of the chip. This highly versatile device enables a wide range of FPGA applications.

Parameters

AttributesValue
Vddc1.05 - 1.15
Vddio1.71 - 3.465
GPIOs (#)32
Look-up Table (LUTs)2240
D Flip-flops (DFFs) (#)2240
BRAM (kbit)64
Distributed Memory (kbit)10
Vddio Domains (#)2
LVDS Channels (#)3
On-chip OscillatorYes
On-chip Oscillator Freq.50MHz / 3MHz
PLLs2
Configuration ModesSPI Controller, SPI Target, OTP
Memory TypeOTP
Temp. Range (°C)-40 to +85°C
Sleep/Reset Mode Current (µA)77
Static State Iddc (µA)118
Special FeaturesSleep Mode,Fast Route,Bitstream AES Decryption,Boot Control

Package Options

Pkg. TypePkg. Dimensions (mm)Lead Count (#)Pitch (mm)
LQFN5.0 x 5.0 0.4 pitch400.4

Applications

  • Consumer electronics
  • Data communications equipment
  • Handheld and portable electronics
  • Notebooks and tablet PCs
  • Industrial instrumentation and control
Part NumberStatusSamplesStockPackageBudgetary Price (USD)Lead Count (#)Temp. Range (°C)
SLG47920VActiveAvailableOut of StockLQFN1ku | $2.5440#-40 to +85°C
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    Recommended Documents (1)

  1. Datasheet
    SLG47920/SLG47921 Datasheet
    RECOMMENDED
    PDF 3.58 MB R19DS0153EU0102 Rev.1.02 Mar 26, 2026
    The SLG47920/SLG47921 are small, low-power devices for common FPGA applications. Users create a circuit design by programming the one-time programmable (OTP) non-volatile memory (NVM) or providing a bitstream through an SPI interface to configure the FPGA core, the IO pins, and the macrocells of the chip. This document describes the main design and operational characteristics of the SLG47920/SLG47921, including pin information, specifications, description, application information, and packaging.

    Datasheets (1)

  1. Datasheet
    SLG47920/SLG47921 Datasheet
    RECOMMENDED
    PDF 3.58 MB R19DS0153EU0102 Rev.1.02 Mar 26, 2026
    The SLG47920/SLG47921 are small, low-power devices for common FPGA applications. Users create a circuit design by programming the one-time programmable (OTP) non-volatile memory (NVM) or providing a bitstream through an SPI interface to configure the FPGA core, the IO pins, and the macrocells of the chip. This document describes the main design and operational characteristics of the SLG47920/SLG47921, including pin information, specifications, description, application information, and packaging.

    Manuals & Guides (1)

  1. Manual - Hardware
    ForgeFPGA Configuration Guide
    PDF 1.94 MB R19US0005EU0250 Rev.2.50 Jan 29, 2026

    Application Notes & White Papers (9)

  1. Application Note
    AN-FG-027 Using Placement Constraints in ForgeFPGA Designs
    PDF 905 KB R19AN0461EU0100 Rev.1.00 Mar 05, 2026
    Placement constraints are used to control where a particular logic block needs to be placed in the floorplan for optimum results. This application note explains how to use the constraint rules or limitations during the physical design phase of the design. It covers the two key aspects of the concept used in setting placement constraints, i.e., placement group and placement region.
    Related Files:
    Sample Code
  2. Application Note
    AN-FG-026 How to Use Full-Chip Simulation in ForgeFPGA Design
    PDF 670 KB R19AN0460EU0100 Rev.1.00 Mar 05, 2026
    The ForgeFPGAs can be used to verify the operation of an entire digital system at the RTL level. This application note describes how to create the Full-Chip Model for a particular design and use it to verify the functionality. This approach makes it possible to trace the interaction between all modules in the silicon and detect potential errors early in the development process before prototyping with actual hardware.
    Related Files:
    Sample Code
  3. Application Note
    AN-FG-023 Shift Register (SRL)
    PDF 530 KB R19AN0455EU0100 Rev.1.00 Feb 17, 2026
    The SLG47921 ForgeFPGA implements LUT‑based shift registers in CLB distributed memory, offering SRL16E, SRL32E, and SRL64E for delay and serial data handling. It covers static and dynamic SRLs, Verilog I/O (i_clk, i_data, i_we, i_addr), synthesis and floorplan steps, and validation in the Logic Analyzer. This document covers static and dynamic SRLs, Verilog I/O (i_clk, i_data, i_we, i_addr), synthesis and floor plan steps, and validation in the Logic Analyzer.
    Related Files:
    Sample Code
  4. Application Note
    AN-FG-032 I2C Controller
    PDF 812 KB R19AN0466EU0100 Rev.1.00 日本語简体中文 Jan 28, 2026
    The versatile and powerful SLG47920/21 device is designed for multi-device I²C communication. The SLG47921's FSM efficiently handles device initialization, data acquisition, and display updates, making it ideal for applications requiring reliable and precise data processing. This application note describes how to use an I²C Controller (also known as Master) to communicate with multiple devices using the ForgeFPGA SLG47920/21 device.
    Related Files:
    Sample Code
  5. Application Note
    AN-FG-029 How to Design Bidirectional LVDS
    PDF 987 KB R19AN0463EU0100 Rev.1.00 简体中文 Jan 28, 2026
    The SLG47920/21 supports bidirectional data transfer using LVDS pairs. It features six LVDS-capable GPIOs, each pair capable of operating as independent CMOS GPIOs or as a single LVDS differential line transceiver pair. The device supports data rates up to 100Mbps and offers configurable options for input, output, and pull-up settings. This application note explains how to connect two LVDS pairs (TX1-RX1 and TX2-RX2) to transfer data using the SLG47920/21 bidirectionally.
    Related Files:
    Sample Code
    6. View More (9)

    Errata & Technical Updates (1)

  1. Device Errata
    SLG47920/21 Errata Note
    PDF 418 KB R19ZZ0023EU0101 Rev.1.01 Dec 09, 2025

    Schematics & Design Files (1)

  1. PCB Design Files
    ForgeFPGA Altium Library
    ZIP 760 KB Dec 23, 2025
    The ForgeFPGA Altium Library is a collection of schematic symbols and physical PCB footprints for Renesas' ForgeFPGA programmable mixed-signal ICs that are available for use within the Altium Designer software environment. The library allows engineers to easily incorporate these devices into their PCB designs using industry-standard CAD tools.

Renesas Boards & Kits

SLG47920V-SKT Socket Card Kit
SLG47920V-SKT Active

ForgeFPGA SLG47920V Socket Card Kit

The SLG47920V-SKT is a socket card kit for use with the SLG4DVKGOCONF Go Configure Development Board. The SLG47920V-SKT kit includes the ForgeFPGA™ Socket Card #4 (SLG7SC4), 20 samples of SLG47920V, and a Pmod™ LED adapter.

The ForgeFPGA™ Socket Card #4 is a development board designed for... Read More

Recommended Documents:
ForgeFPGA™ Socket Card #4 User Manual
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Go Configure Development Board
SLG4DVKGOCONF Active

Go Configure Development Board

The Go Configure™ Development Board is a universal development board for Renesas' ForgeFPGA products that supports all features of the Go Configure™ Software Hub. A set of compatible socket cards is available for a quick and easy start to the development process. This board is ideal for rapid... Read More

Recommended Documents:
Go Configure™ Development Board User Manual
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    Software & Tools (2)

  1. Software Package
    Go Configure Software Hub
    Go Configure Software Hub provides development support for a variety of products, including GreenPAK configurable mixed signal matrix and ForgeFPGA™ devices.
  2. PCB Design Files
    ForgeFPGA Altium Library
    ZIP 760 KB Dec 23, 2025
    The ForgeFPGA Altium Library is a collection of schematic symbols and physical PCB footprints for Renesas' ForgeFPGA programmable mixed-signal ICs that are available for use within the Altium Designer software environment. The library allows engineers to easily incorporate these devices into their PCB designs using industry-standard CAD tools.
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  1. SLG47910 ForgeFPGA IC Availability in 2025

    The evaluation board for the SGL47910 is available, but purchasing units of the IC in less than reel qty (100..200 units) seems an impossible task, and I don't want to design something only to find out I'd be required to purchase 5000 units. When is this IC ...

    Feb 6, 2025
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