Skip to main content
Renesas Electronics Corporation - June is Pride Month, a month to raise awareness of the rights and the culture of the LGBTQ+ community

Features

  • Dense array of configurable logic
    • 1120 5-bit LUTs
    • 1120 D-type flip flops (DFFs)
    • 5kb distributed memory
    • 32kb block random access memory (BRAM)
  • Power supply domains
    • Two separate domains (20 GPIOs per domain)
    • VDDIO0 and VDDIO1: 1.71V to 3.465V
    • VDDC: 1.1V ± 5%
  • Clocking
    • High-frequency oscillator
      • 50MHz high-frequency oscillator
    • Oscillator post divider
      • Divide oscillator clock by a power of 2 (range 1 to 128)
      • Two independent outputs
    • Phase-locked loop (PLL)
      • Input from an external source, internal oscillator, or LVDS differential clock
  • Power-on reset (POR)
  • Flexible power-consumption control
    • FPGA core power control
    • Clock sources power control
    • BRAM deep-sleep/power-gated modes
  • General-purpose IOs
    • 40 GPIOs
    • Flexible configuration options
      • Selectable drive strength (4/8/12mA)
      • Optional pull-up – 1x or 2x
      • Optional pull-up control from the FPGA core
      • Optional Schmitt trigger input
    • Six LVDS-capable GPIOs (three true-LVDS pairs up to 100Mbps)
    • Fast routing capability between pairs of GPIO located in different IO voltage domains
  • Bitstream security features
    • CRC integrity check
    • AES decryption
  • Configuration options
    • OTP mode – Load from built-in OTP memory
    • SPI Controller (Master) mode – Load from external Flash memory
    • SPI Target (Slave) mode – Load from external source (MCU host)
  • Boot control logic: Can address up to 16 different bitstreams from external memory
  • Two idle low-power modes
    • Sleep mode when configuration is being retained and no device re-configuration is needed
    • Reset mode when device re-configuration is required after exit from this mode
    • Possibility to retain GPIOs and BRAM states in both low-power modes
    • Low power consumption in both modes (< 85µA)
  • Operating temperature range: -40°C to 85°C
  • RoHS-compliant/Halogen-free
  • Available packages
    • SLG47912V: 48-pin QFN: 6.0mm x 6.0mm, 0.4mm pitch
    • SLG47912C: 48-pin WLCSP: 3.24mm x 2.57mm, 0.35mm pitch  

Description

The SLG47912 is a small, low-power device for common FPGA applications. Users create a circuit design by programming the one-time programmable (OTP) non-volatile memory (NVM) or providing a bitstream through an SPI interface to configure the FPGA core, the IO pins, and the macrocells of the chip. This highly versatile device enables a wide range of FPGA applications.

Parameters

AttributesValue
Vddc1.05 - 1.15
Vddio1.71 - 3.465
GPIOs (#)40
Look-up Table (LUTs)1120
D Flip-flops (DFFs) (#)1120
BRAM (kbit)32
Distributed Memory (kbit)5
Vddio Domains (#)2
LVDS Channels (#)3
On-chip OscillatorYes
On-chip Oscillator Freq.50MHz / 3MHz
PLLs1
Configuration ModesSPI Controller, SPI Target, OTP
Memory TypeOTP
Temp. Range (°C)-40 to +85°C
Sleep/Reset Mode Current (µA)77
Static State Iddc (µA)118
Special FeaturesSleep Mode,Fast Route,Bitstream AES Decryption,Boot Control

Package Options

Pkg. TypePkg. Dimensions (mm)Lead Count (#)Pitch (mm)
LQFN6.0 x 6.0 0.4 pitch480.4
WLCSP3.241 x 2.575 0.35 pitch48

Applications

  • Consumer electronics
  • Data communications equipment
  • Handheld and portable electronics
  • Notebooks and tablet PCs
  • Industrial instrumentation and control
Part NumberStatusSamplesLongevityStockPackageBudgetary Price (USD)Lead Count (#)Temp. Range (°C)
SLG47912CActiveAvailableOut of StockWLCSP1ku | $2.0548#-40 to +85°C
SLG47912VActiveAvailable2041 JanOut of StockLQFN1ku | $2.0548#-40 to +85°C

Renesas Boards & Kits

Knowledge Base

  1. Can I use SPI Flash from another vendor?

    ... read: 0Bh Power-down or deep-sleep: B9h Should exit power-down or deep sleep mode in less than 300us Required Flash memory capacity depends on used device: for SLG47910 it is at least 384kbit; for SLG47912/20/21 it is at least 769kbit.   Suitable Products ForgeFPGA™

    Mar 25, 2026
  2. What drive strength options are available for GPOs?

    Last Updated: 03/25/2026 Question: What drive strength options are available for GPOs? Answer: In SLG47910 two drive strength options available: 4/8 mAIn SLG47912, SLG47920, SLG47921 three drive strength options available - 4/8/12 mA   Suitable Products ForgeFPGA™

    Mar 25, 2026
  3. Is it possible to initialize the BRAM block?

    Last Updated: 03/25/2026 Question: Is it possible to initialize the BRAM block? Answer: BRAM initialization is not supported on the SLG47910. However, it is supported on the SLG47912, SLG47920, and SLG47921.   Suitable Products ForgeFPGA™

    Mar 25, 2026
View All Results from Knowledge Base (6)
Support Communities

Support Communities

Get quick technical support online from Renesas Engineering Community technical staff.
Browse Articles

Knowledge Base

Browse our knowledge base for helpful articles, FAQs, and other useful resources.
Submit a Ticket

Submit a Ticket

Need to ask a technical question or share confidential information?