Overview
Description
The SH7239 Series is a high-end single chip microcontroller incorporating an SH-2A core that offers a maximum operating frequency of 160MHz. The SH7239 Series lineup consists of the SH7239 group (with floating-point unit (FPU)) and the SH7237 group (without FPU). The SH7237/SH7239 group incorporates various peripheral function suitable for industrial application AC servos, general-purpose inverters and robots, such as a 16-bit multifunction timer unit(MTU2/MTU2S) and a 12-bit A/D converter, etc.& In comparison with a conventional product, maximum operating frequency of MTU2 was improved. (3.3V version: max 80MHz, 5V version: max 100MHz) The SH7237/SH7239 group incorporates 512KB flash memory and 64KB RAM in addition to 32KB flash memory for data storage. The SH7237/SH7239 group also incorporates various interfaces such as a CAN, 4 channel Serial interface, RSPI etc.
Comparison
Applications
Design & Development
Software & Tools
Sample Code
Models
ECAD Models
Schematic symbols, PCB footprints, and 3D CAD models from SamacSys can be found by clicking on the CAD Model links in the Product Options table. If a symbol or model isn't available, it can be requested directly from SamacSys.
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FAQs
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How to write to the internal flash memory with the MCU in boot mode?
Please check the following points. ・Power-on reset is correct. ‐Reset signal is cleared after the oscillation is stabilized at the time of power-on. ‐The hardware stand-by pin (HSTBY) is not switched to Low at power-on if your MCU has a stand-by function. ・The mode pin ...
Sep 9, 2011 -
What will happen if TFRST and RFRST in SCFCR of SCIF with FIFO is set to 1?
When TFRST is 1, the transmit FIFO data register (SCFTDR) is reset, however, the transmit shift register (SCTSR) continues the operation. Therefore the transmit data that has already been transferred to the SCTSR will be transmitted. When RFRST is 1, the receive FIFO data register (SCFERDR) is reset, but the ...
Mar 21, 2012 -
Is fractional portion 0.5 cycle equivalent to standard value 1/2tcyc?
2 cycles are added to the Th when 10:2.5 cycle is set to the SW[1:0] bit, and 2 cycles are added to the Tf when 10:2.5 cycle is set to the HW[1:0] bit. As you mentioned.
Sep 11, 2012