RJP1C15JWS

AI-generated Summary: Wire bonding damage occurs during the assembly of bare die or wafer IGBTs when improper bonding conditions cause defects such as misaligned bonds, chip surface scratches, or cracks. Excessive bonding stress can damage cells visibly or internally, affecting device performance and reliability. Evaluating bonding limits by adjusting power and force ensures optimal bonding strength without damage. Careful verification of bonding conditions improves yield and prevents failures like turn-off malfunctions caused by localized damage.

AI-generated Summary: Gate drive conditions for IGBT and FRD devices focus on optimizing gate voltage, drive current, and gate resistor selection to ensure efficient switching performance and device protection. Recommended gate voltage is 15 V for turn-on, with off-state voltage set negative to prevent false turn-on. Increasing gate voltage reduces saturation voltage but shortens short-circuit withstand time, requiring balance. Drive current must be sufficient to charge/discharge the gate for fast switching. Gate resistor impacts switching time, loss, surge voltage, false turn-on, and ringing noise; selecting appropriate resistor values for turn-on and turn-off improves performance. Switching time increases with gate resistance, influencing device operation and efficiency.

AI-generated Summary: The document details procedures for assembling IGBT modules, emphasizing proper installation order to prevent damage and ensure reliability. It covers mounting methods for pin-fin copper base and flat copper base modules, focusing on cooling water channel design, O-ring sealing for watertightness, and corrosion prevention. It highlights the importance of minimizing gaps in cooling channels to maximize flow velocity and prevent leakage. The document also discusses thermal grease application for flat copper base modules and recommends testing for leakage resistance and galvanic corrosion to ensure long-term durability.

AI-generated Summary: The document details specifications and usage guidelines for a 6-in-1 IGBT module designed for 3-phase inverters in xEV applications. It covers the module's structure, including IGBTs, FRDs, and thermistors, and explains cooling methods using flat or pin-finned copper bases with water or grease cooling. The document highlights thermal fatigue concerns due to material expansion differences and provides detailed datasheet parameters for IGBTs and FRDs, including absolute maximum ratings and electrical characteristics essential for safe and reliable operation.

AI-generated Summary: Wafer testing for IGBT chips bridges the gap between wafer-level and module-level testing by applying higher test currents closer to module conditions, improving overall module quality. Key failure modes include gate failure, detected through high-voltage DC screening to identify oxide defects, and SOA failure, identified via AC switching tests to detect transient current concentration and latch-up failures. Gate screening applies stress beyond normal operation to reduce early failures and ensure long-term reliability. L-load AC screening rejects chips prone to latch-up by simulating switching conditions, enhancing yield and reducing costs in module manufacturing.

AI-generated Summary: Surge voltage occurs at IGBT turn-off, increasing with low gate resistance or high di/dt. Increasing gate resistance reduces surge but risks switching failure. Renesas IGBTs suppress surge voltage by enabling a self-clamping mode at low gate resistance (e.g., 4 ohms or less). This mechanism involves rapid channel closure, increased hole carriers maintaining current, and gradual hole carrier disappearance, which clamps voltage. The design ensures robustness, maintaining safe operation even at three times rated current and low gate resistance. Key switching parameters and measurement circuits are also detailed.

AI-generated Summary: Failure chip mapping data for IGBT wafer products uses an electronic format called the e-wafer map. The e-wafer map provides detailed failure area information, including wafer ID, lot number, chip size, and pass/fail status for each chip. The format is XML-based and includes coordinates and mapping data to visualize failure locations on wafers. This data supports wafer production flow and quality control by clearly identifying defective chips and their positions.

AI-generated Summary: The document explains methods to measure load short circuits (LSC) in IGBTs, distinguishing between arm short circuits occurring inside the inverter and load shorts at the output. It details causes of arm shorts, such as simultaneous high-side and low-side activation, overlapping switching times, and high dv/dt effects, with countermeasures like adjusting deadtime and gate resistance. For load shorts, it presents two protection methods: using IGBTs with short circuit withstand capability and leveraging output inductance to delay current rise. The LSC test methodology includes specific test conditions and waveform monitoring to validate IGBT robustness under short circuit conditions.

AI-generated Summary: Packing specifications for IGBT wafer products include detailed procedures for both sawn and unsawn wafers. Sawn wafers are wrapped with UV foil and undergo UV irradiation before shipping, eliminating the need for further UV treatment by customers. Labels indicating wafer information are placed according to specified areas. Photos illustrate packing samples, including failure-marked and inkless wafers. Unsawn wafers are packed with protective sheets, also UV irradiated, and positioned with the bottom side facing up, ensuring no additional UV process is required by customers.

AI-generated Summary: Long-term storage of IGBT wafers, including sawn wafers, does not degrade die pickup intensity or solderability under various conditions such as room temperature storage up to 18 months, and high/low temperature tests. Adhesion between dicing tape and wafer remains stable, and no adhesive residue affects soldering quality. Evaluations cover die sizes 8.8mm x 8.8mm and 14mm x 14mm, confirming reliable pickup and solder spread performance throughout storage periods.

AI-generated Summary: The document outlines derating standards for Power MOSFETs and IGBTs, emphasizing temperature, humidity, voltage, current, and power limits to ensure device reliability. It discusses package type selection between hermetic sealed and plastic molded types, highlighting the advantages of surface-mount packages for miniaturization. It also details precautions for physical handling, including proper lead forming, cutting, and mounting techniques to prevent stress and damage during installation.

AI-generated Summary: When connecting IGBTs in parallel, current unbalance occurs due to differences in VCE(sat) and parasitic resistances in the wiring and board. This unbalance affects device loss and switching behavior. Minimizing VCE(sat) variation by using devices from the same production lot and designing symmetrical layouts reduces unbalance. Gate driver emitter-sense wiring must also be symmetrical to ensure equal gate voltages. Temperature dependence of VCE(sat) influences current sharing, with positive temperature dependence improving stability.

AI-generated Summary: The document defines absolute maximum ratings for IGBTs, including voltage, current, power dissipation, and temperature limits to ensure safe operation. It details electrical characteristics such as leakage currents, capacitances, switching times, and energy losses. Collector current and dissipation depend on temperature and voltage, with formulas provided for calculation. Users must operate IGBTs within specified maximum ratings to maintain reliability.