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Renesas Electronics Corporation

Renesas’ Timing product portfolio has been acquired by SiTime.

Datasheets, documentation, and sample orders remain available on Renesas.com through late 2026. For new designs, purchasing, support, and product inquiries, visit SiTime.com or send an email to [email protected]. Full transition to SiTime is expected by late 2026.

Features

  • Low power, less than 1.4W typical
  • Low jitter, less than 100fs RMS
  • PCIe Gen 1-6 CC, SRIS, and SRNS support
  • Up to six fractional output dividers and 12 integer output dividers
  • Each fractional output divider is free-run and locked to APLL
  • Each fractional output divider can be configured as NCO or DCO
  • LVCMOS, LVPECL, LVDS, HCSL, CML, SSTL, and HSTL output modes supported with programmable output swing and common mode voltage
  • One crystal/XO input
  • Up to nine GPIO pins programmable to device select or system monitor options
  • Supports 1MHz I²C, 400kHz SMBus, or 50MHz SPI serial port
  • Internal non-volatile memory (up to 16 different configurations), or external serial I²C EEPROM provide default device settings on power up.
  • 2.5V and 3.3V core and 1.8V, 2.5V, and 3.3V output operation
  • -40 °C to +85 °C industrial temperature operation

Description

The RC22112A regenerates and distributes ultra-low jitter clock outputs and features up to six independent frequency domains that can be locked to a free-run crystal or oscillator. The device supports multiple independent reference clocks for high-speed serial links. Input-to-input, input-to-output, and output-to-output phase skew can all be precisely managed. The device outputs ultra-low-jitter clocks that can directly synchronize SerDes running at up to 56Gbps. The device is ideal for use in 100G/200G/400G/800G telecom switch fabric cards and OTN applications.

Parameters

AttributesValue
Product CategoryFemtoClock

Package Options

Pkg. TypePkg. Dimensions (mm)Lead Count (#)Pitch (mm)
QFN72
VFQFPN10.0 x 10.0 x 1.0720.5

Application Block Diagrams

Vehicle Computer for Future E/E Architecture Block Diagram
Vehicle Computer for Future E/E Architecture
Next-generation vehicle computer system for advanced E/E architecture with high computing power.

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