Features
- PCIe Gen 1–7 compliance
- 2:8 multiplexer or two 4-output buffer options
- Drive both source-terminated and double-terminated loads
- Selectable 34Ω, 85Ω, and 100Ω output impedance
- Power down tolerance (PDT)
- Flexible startup sequencing (FSS)
- Automatic clock parking (ACP)
- Dedicated OE# pins to control group output
- 6mm × 6mm 48-VFQFPN package
Description
The RC19308 is a 2:8 PCIe Gen7 multiplexer that is backward compatible with earlier PCIe generations. The RC19308 provides ultra-low additive jitter and reduced in-to-out delay performance for better design margin and incorporates several features for easier and more robust design.
Parameters
| Attributes | Value |
|---|---|
| Temp. Range (°C) | -40 to 105°C, -40 to 105°C (Tc ≤ 105°C) |
Package Options
| Pkg. Type | Pkg. Dimensions (mm) | Lead Count (#) | Pitch (mm) |
|---|---|---|---|
| VFQFPN | 6.0 x 6.0 x 0.9 | 48 | 0.4 |
Applications
- Cloud/High-performance computing
- nVME storage
- Networking
- Accelerators
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Software & Tools
Sample Code
Simulation Models
The RC family consists of PCIe Gen7 clock buffer and multiplexer solutions, providing the industry's smallest and most compact footprint.
A detailed overview of IDT's full-featured PCI Express (PCIe) clock and timing solutions. The presentation addresses PCIe Gen 1, Gen 2, Gen 3, and Gen 4 architectures and how IDT's industry-leading solutions provide all the functions, features, and performance required by the application.
Presented by Ron Wade, System Architect at IDT. For more information visit the PCIe clocks page.
A brief overview of the PCI Express common clock (CC) jitter model, and the transfer functions as they relate to the timing PLLs. This model applies to PCI Express (PCIe) Gen 2, Gen 3, Gen 4 and Gen 5. The equations would be slightly different for other PCIe architectures, such as SRIS, SRnS, or data clocked.
Presented by Ron Wade, system architect at IDT (acquired by Renesas). For more information about Renesas's PCIe timing solutions, visit the PCI Express (PCIe) Clocks page.
This video compares PCIe Gen3–7 common clock jitter filters with a typical 12kHz to 20MHz plot to highlight the differences in filtering approaches.