Features
- Can be used for an analog transceiver for the following interfaces:
- Universal Serial Bus Specification Revision 2.0
- Battery Charging Specification Revision 1.2
- Technology is TSMC's 40nm Low Power (LP) 1p7M/1p8M
- Supply voltage can be applied - 1.1V for core voltage and 3.3V for I/O voltage
- USB transfer mode is High-Speed (480Mbps), Full-Speed (12Mbps), and Low-Speed (1.5Mbps) modes
- A terminal resistance, pull-up resistor, and pull-down resistor are included
- Input reference clock is 48MHz, 24MHz, 20MHz, and 12MHz
USB 2.0 PHY for Single-Port Transceiver IP (TSMC 40nm LP) Block Diagram
Description
Renesas' USB 2.0 Transceiver IP is a useful analog single-port transceiver hard macro for UTMI+ (USB 2.0 Transceiver Macrocell Interface +) Level 3. Fabricated using TSMC's 40nm Low Power (LP) process, this macro can be configured to operate as a USB 2.0 peripheral or USB 2.0 host controller.
Parameters
| Attributes | Value |
|---|---|
| Protocol | USB 2.0 |
| Function | PHY, Transceiver |
| Process | TSMC 40nm LP |
| Data Rate (Mbps) | 480, 12, 1.5 |
| Interface | UTMI+ |
| Number of Channels | 1 |
| Input Freq (MHz) | 48 - 48, 24 - 24, 20 - 20, 12 - 12 |
| Supply Voltage Range (V) | Core: 1.1V, I/O: 3.3V |
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