Features
- Single 1.7V - 2.0V Supply
- 128Mbit (16 x 8 Mbit physical block) Flash Memory
- Serial Peripheral Interface (SPI) and Quad Peripheral Interface (QPI) Compatible
- Supports SPI Modes 0 and 3
- Supports Dual Output Read and Quad I/O Program and Read
- Supports QPI Program and Read
- 133MHz Maximum Operating Frequency
- Clock-to-Output (tV1 ) of 6ns
- Up to 65Mbytes/s Continuous Data Transfer Rate
- Quad Enabled
- Full Chip Erase
- Flexible, Optimized Erase Architecture for Code and Data Storage Applications
- 0.6ms Typical Page Program (256 bytes) Time
- 60ms Typical 4kB Block Erase Time
- 200ms Typical 32kB Block Erase Time
- 350ms Typical 64kB Block Erase Time
- Hardware Controlled Locking of Status Registers via WP Pin
- 4kbit Secured One-Time Programmable Security Register
- Hardware Write Protection
- Serial Flash Discoverable Parameters (SFDP) Register
- Flexible Programming
- Byte/Page Program (1 to 256 bytes)
- Dual or Quad Input Byte/Page Program (1 to 256 bytes)
- Erase/Program Suspend and Resume
- JEDEC Standard Manufacturer and Device ID Read Methodology
- Low Power Dissipation
- 2μA Deep Power-Down Current (Typical)
- 10μA Standby Current (Typical)
- 5mA Active Read Current (Typical)
- Endurance: 100,000 program/erase cycles (4kbyte, 32kbyte, or 64kbyte blocks)
- Data Retention: 20 Years
- Industrial Temperature Range: -40°C to +85°C
- Industry Standard Green (Pb/Halide-free/RoHS-Compliant) Package Options
- 8-Pad DFN (6mm x 5mm x 0.6mm)
- 8-Lead SOIC (208mil)
- 21-Ball WLCSP
- 21-Ball Low-Profile WLCSP
Description
The AT25QL128A is a member of our standard class code and data storage solutions designed for low-voltage systems in which program code is shadowed from Flash memory into embedded or external RAM for execution.
The architecture includes standard erase block sizes and a security register for unique device serialization, system-level Electronic Serial Number (ESN) storage, locked key storage, etc.
The AT25QL128A is Quad enabled at the factory and offers a universally compatible pinout and command set, standard block architecture, and continuous read, wrap, and burst modes for XiP.
Parameters
| Attributes | Value |
|---|---|
| Memory Class | Standard Flash |
| Memory Density | 128 Mbit |
| Operating Voltage Range (V) | 1.7 - 2 |
| Speed | 133 MHz |
| Interface | Quad SPI (default), Single, Dual |
| Temp. Range (°C) | -40 to +85°C |
| Deep Power Down (µA) | 2 |
| Read Current (mA) | 7 |
| Key Benefit | Standard features |
Package Options
| Pkg. Type | Pkg. Dimensions (mm) | Pitch (mm) |
|---|---|---|
| See Wafer-Die Solution Menu | — | — |
| UDFN | 5 x 6 | 1.27 |
| WLCSP | — | — |
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