Features
- Can be used for an analog transmitter/receiver for the following interfaces:
- MIPI Alliance Specification for D-PHY Version 2.1 15 December 2016
- MIPI Alliance Specification for DSI (Display Serial Interface)
- MIPI Alliance Specification for CSI-2 (Camera Serial Interface 2)
- Technology is TSMC's 22nm ULL (Ultra-Low Leakage) 1p9M.
- Supply voltage can be applied - 1.1V for core voltage, 1.8V and 3.3V for I/O voltage
- Maximum data rate of each channel is 1.2Gbps in High-Speed mode
MIPI D-PHY Transceiver for CSI-2/DSI IP (TSMC 22nm ULL) Block Diagram
Description
Renesas' MIPI® D-PHY™ Transmitter/Receiver IP is a 2 data lanes transmitter/receiver hard macro for DSI℠/CSI-2®, fabricated using TSMC's 22 ULL (Ultra-Low Leakage) process.
Parameters
| Attributes | Value |
|---|---|
| Protocol | MIPI |
| Function | D-PHY, Transceiver |
| Process | Soft macro & TSMC 22nm ULL |
| Data Rate (Mbps) | 1200 |
| Interface | CSI-2, DSI, PPI |
| Number of Channels | 2 |
| Supply Voltage Range (V) | Core: 1.1V, I/O: 1.8 and 3.3V |
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